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77c93881e7
Summary: Add getMemOpBaseRegImmOfsWidth to enable determining independence during MiSched. Reviewers: eliben, majnemer Subscribers: mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D18903 llvm-svn: 266338
138 lines
4.5 KiB
C++
138 lines
4.5 KiB
C++
//===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Lanai implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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#define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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#include "LanaiRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "LanaiGenInstrInfo.inc"
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namespace llvm {
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class LanaiInstrInfo : public LanaiGenInstrInfo {
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const LanaiRegisterInfo RegisterInfo;
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public:
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LanaiInstrInfo();
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// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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// such, whenever a client has an instance of instruction info, it should
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// always be able to get register info as well (through this method).
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virtual const LanaiRegisterInfo &getRegisterInfo() const {
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return RegisterInfo;
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}
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bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb,
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AliasAnalysis *AA) const override;
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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DebugLoc DL, unsigned DestinationRegister,
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unsigned SourceRegister, bool KillSource) const override;
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void
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storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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unsigned SourceRegister, bool IsKill, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const override;
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void
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loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator Position,
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unsigned DestinationRegister, int FrameIndex,
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const TargetRegisterClass *RegisterClass,
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const TargetRegisterInfo *RegisterInfo) const override;
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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bool getMemOpBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
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int64_t &Offset,
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const TargetRegisterInfo *TRI) const override;
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bool getMemOpBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned &BaseReg,
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int64_t &Offset, unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
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MachineBasicBlock *&FalseBlock,
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SmallVectorImpl<MachineOperand> &Condition,
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bool AllowModify) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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bool ReverseBranchCondition(
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SmallVectorImpl<MachineOperand> &Condition) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
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MachineBasicBlock *FalseBlock,
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ArrayRef<MachineOperand> Condition,
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DebugLoc DL) const override;
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};
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static inline bool isSPLSOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDBs_RI:
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case Lanai::LDBz_RI:
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case Lanai::LDHs_RI:
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case Lanai::LDHz_RI:
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case Lanai::STB_RI:
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case Lanai::STH_RI:
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return true;
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default:
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return false;
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}
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}
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static inline bool isRMOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDW_RI:
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case Lanai::SW_RI:
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return true;
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default:
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return false;
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}
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}
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static inline bool isRRMOpcode(unsigned Opcode) {
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switch (Opcode) {
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case Lanai::LDBs_RR:
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case Lanai::LDBz_RR:
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case Lanai::LDHs_RR:
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case Lanai::LDHz_RR:
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case Lanai::LDWz_RR:
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case Lanai::LDW_RR:
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case Lanai::STB_RR:
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case Lanai::STH_RR:
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case Lanai::SW_RR:
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return true;
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default:
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return false;
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}
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}
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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