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58c47fb118
This patch upstreams support for the Armv8.6-a Matrix Multiplication Extension. A summary of the features can be found here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a This patch includes: - Assembly support for AArch32 and Assembly Parsing D77872 has already added the MC representations of the instructions so that they can be used in code gen; this patch fills in the details needed to make assembly parsing work, and adds tests for asm and disasm This is part of a patch series, starting with BFloat16 support and the other components in the armv8.6a extension (in previous patches linked in phabricator) Based on work by: - Luke Geeson - Oliver Stannard - Luke Cheeseman Reviewers: t.p.northover, simon_tatham Reviewed By: simon_tatham Subscribers: simon_tatham, ostannard, kristof.beyls, hiraditya, danielkiss, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D77874
50 lines
2.8 KiB
ArmAsm
50 lines
2.8 KiB
ArmAsm
// RUN: llvm-mc -triple armv8a -show-encoding -mattr=+i8mm < %s | FileCheck %s --check-prefix=ARM
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// RUN: llvm-mc -triple thumbv8a -show-encoding -mattr=+i8mm < %s | FileCheck %s --check-prefix=THUMB
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// RUN: not llvm-mc -triple armv8a -show-encoding -mattr=v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMATMUL
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// RUN: not llvm-mc -triple thumbv8a -show-encoding -mattr=v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMATMUL
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vsmmla.s8 q0, q1, q2
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// ARM: vsmmla.s8 q0, q1, q2 @ encoding: [0x44,0x0c,0x22,0xfc]
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// THUMB: vsmmla.s8 q0, q1, q2 @ encoding: [0x22,0xfc,0x44,0x0c]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vummla.u8 q0, q1, q2
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// ARM: vummla.u8 q0, q1, q2 @ encoding: [0x54,0x0c,0x22,0xfc]
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// THUMB: vummla.u8 q0, q1, q2 @ encoding: [0x22,0xfc,0x54,0x0c]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vusmmla.s8 q0, q1, q2
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// ARM: vusmmla.s8 q0, q1, q2 @ encoding: [0x44,0x0c,0xa2,0xfc]
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// THUMB: vusmmla.s8 q0, q1, q2 @ encoding: [0xa2,0xfc,0x44,0x0c]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vusdot.s8 d0, d1, d2
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// ARM: vusdot.s8 d0, d1, d2 @ encoding: [0x02,0x0d,0xa1,0xfc]
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// THUMB: vusdot.s8 d0, d1, d2 @ encoding: [0xa1,0xfc,0x02,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vusdot.s8 q0, q1, q2
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// ARM: vusdot.s8 q0, q1, q2 @ encoding: [0x44,0x0d,0xa2,0xfc]
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// THUMB: vusdot.s8 q0, q1, q2 @ encoding: [0xa2,0xfc,0x44,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vusdot.s8 d0, d1, d2[0]
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// ARM: vusdot.s8 d0, d1, d2[0] @ encoding: [0x02,0x0d,0x81,0xfe]
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// THUMB: vusdot.s8 d0, d1, d2[0] @ encoding: [0x81,0xfe,0x02,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vsudot.u8 d0, d1, d2[1]
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// ARM: vsudot.u8 d0, d1, d2[1] @ encoding: [0x32,0x0d,0x81,0xfe]
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// THUMB: vsudot.u8 d0, d1, d2[1] @ encoding: [0x81,0xfe,0x32,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vusdot.s8 q0, q1, d2[0]
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// ARM: vusdot.s8 q0, q1, d2[0] @ encoding: [0x42,0x0d,0x82,0xfe]
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// THUMB: vusdot.s8 q0, q1, d2[0] @ encoding: [0x82,0xfe,0x42,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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vsudot.u8 q0, q1, d2[1]
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// ARM: vsudot.u8 q0, q1, d2[1] @ encoding: [0x72,0x0d,0x82,0xfe]
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// THUMB: vsudot.u8 q0, q1, d2[1] @ encoding: [0x82,0xfe,0x72,0x0d]
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// NOMATMUL: [[@LINE-3]]:{{[0-9]+}}: error: instruction requires: 8-bit integer matrix multiply
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