Simon Tatham bc23ee33a0 [clang] Use i64 for the !srcloc metadata on asm IR nodes. ... This is part of a patch series working towards the ability to make SourceLocation into a 64-bit type to handle larger translation units. !srcloc is generated in clang codegen, and pulled back out by llvm functions like AsmPrinter::emitInlineAsm that need to report errors in the inline asm. From there it goes to LLVMContext::emitError, is stored in DiagnosticInfoInlineAsm, and ends up back in clang, at BackendConsumer::InlineAsmDiagHandler(), which reconstitutes a true clang::SourceLocation from the integer cookie. Throughout this code path, it's now 64-bit rather than 32, which means that if SourceLocation is expanded to a 64-bit type, this error report won't lose half of the data. The compiler will tolerate both of i32 and i64 !srcloc metadata in input IR without faulting. Test added in llvm/MC. (The semantic accuracy of the metadata is another matter, but I don't know of any situation where that matters: if you're reading an IR file written by a previous run of clang, you don't have the SourceManager that can relate those source locations back to the original source files.) Original version of the patch by Mikhail Maltsev. Reviewed By: dexonsmith Differential Revision: https://reviews.llvm.org/D105491		2021-07-22 10:24:52 +01:00
..
AlignedBundling
Inputs
Windows
2010-11-30-reloc-movt.s
2013-03-18-Br-to-label-named-like-reg.s
align_arm_2_thumb.s
align_thumb_2_arm.s
aligned-blx.s
arm11-hint-instr.s
arm_addrmode2.s
arm_addrmode3.s
arm_fixups.s
arm_instructions.s
arm-aliases.s
arm-arithmetic-aliases.s
arm-branch-errors.s
arm-branches.s
arm-elf-relocation-diagnostics.s
arm-elf-relocations.s
arm-elf-symver.s
arm-it-block.s
arm-ldrd.s
arm-load-store-multiple-deprecated.s
arm-macho-calls.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
arm-memory-instructions-immediate.s	[ARM] support symbolic expression as immediate in memory instructions	2021-04-12 12:13:55 -07:00
arm-memory-instructions.s
arm-qualifier-diagnostics.s
arm-reg-addr-errors.s
arm-shift-encoding.s
arm-thumb-cpus-default.s
arm-thumb-cpus.s
arm-thumb-tail-call.ll
arm-thumb-trustzone.s
arm-trustzone.s
armv8.2a-dotprod-a32.s
armv8.2a-dotprod-error.s
armv8.2a-dotprod-t32.s
armv8.3a-js.s
armv8.4a-trace-error.s
armv8.4a-trace.s
armv8.5a-sb-error-thumb.s
armv8.5a-sb-error.s
armv8.5a-sb.s
armv8.6a-matmul-error.s
armv8.6a-matmul.s
armv8a-fpmul-error.s
armv8a-fpmul.s
assembler-fill.s
assembly-default-build-attributes.s
basic-arm-instructions-v8.1a.s
basic-arm-instructions-v8.s
basic-arm-instructions.s
basic-thumb2-instructions-v8.s
basic-thumb2-instructions.s	[MC][ARM] add .w suffixes for RSB/RSBS T1	2021-04-01 10:45:37 -07:00
basic-thumb-instructions.s
bfloat16-a32-errors2.s
bfloat16-a32-errors.s
bfloat16-a32.s
bfloat16-t32-errors.s
bfloat16-t32.s
big-endian-arm-fixup.s
big-endian-thumb2-fixup.s
big-endian-thumb-fixup.s
bkpt.s
bracket-darwin.s
bracket-exprs.s
branch-disassemble.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
cde-fp-vec.s
cde-integer.s
cde-vec-pred.s
CheckDataSymbol.s
clrm-asm.s
cmp-immediate-fixup2.s
cmp-immediate-fixup-error2.s
cmp-immediate-fixup-error.s
cmp-immediate-fixup.s
coff-debugging-secrel.ll
coff-file.s
coff-function-type-info.ll
coff-relocations.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
comment.s
complex-operands.s
coproc-diag.s
coprocessors.s
cps.s
cpu-test.s
crc32-thumb.s
crc32.s
cxx-global-constructor.ll
d16.s
data-in-code.ll
deprecated-v8.s
dfb-neg.s
dfb.s
diagnostics-noneon.s
diagnostics.s
directive_parsing.s	[MC] Add parseEOL() overload and migrate some parseToken(AsmToken::EndOfStatement) to parseEOL()	2021-03-06 17:45:23 -08:00
directive-align.s
directive-arch_extension-aes-sha2.s	[ARM][AArch64] Require appropriate features for crypto algorithms	2021-04-28 16:26:18 +01:00
directive-arch_extension-crc.s
directive-arch_extension-crypto.s	[ARM][AArch64] Require appropriate features for crypto algorithms	2021-04-28 16:26:18 +01:00
directive-arch_extension-fp.s
directive-arch_extension-idiv.s
directive-arch_extension-mode-switch.s
directive-arch_extension-mp.s
directive-arch_extension-sec.s
directive-arch_extension-simd.s
directive-arch_extension-toggle.s
directive-arch_extension-unsupported.s
directive-arch-armv2.s
directive-arch-armv2a.s
directive-arch-armv3.s
directive-arch-armv3m.s
directive-arch-armv4.s
directive-arch-armv4t.s
directive-arch-armv5.s
directive-arch-armv5t.s
directive-arch-armv5te.s
directive-arch-armv6-m.s
directive-arch-armv6.s
directive-arch-armv6k.s
directive-arch-armv6t2.s
directive-arch-armv6z.s
directive-arch-armv7-a.s
directive-arch-armv7-m.s
directive-arch-armv7-r.s
directive-arch-armv7.s
directive-arch-armv7a.s
directive-arch-armv7e-m.s
directive-arch-armv7em.s
directive-arch-armv7m.s
directive-arch-armv7r.s
directive-arch-armv8-a.s
directive-arch-armv8.2-a.s
directive-arch-armv8a.s
directive-arch-armv8m.s
directive-arch-iwmmxt2.s
directive-arch-iwmmxt.s
directive-arch-mode-switch.s
directive-arch-semantic-action.s
directive-arch-xscale.s	[llvm][ARM] Treat xscale arch as an alias of armv5te	2021-06-28 15:20:24 +00:00
directive-cpu.s
directive-eabi_attribute-diagnostics.s
directive-eabi_attribute-overwrite.s
directive-eabi_attribute.s
directive-even.s
directive-fpu-diagnostics.s
directive-fpu-instrs.s
directive-fpu-multiple.s
directive-fpu-softvfp.s
directive-fpu.s
directive-if-subtraction.s
directive-literals.s
directive-object_arch-2.s
directive-object_arch-3.s
directive-object_arch-diagnostics.s
directive-object_arch.s
directive-thumb_func.s
directive-tlsdescseq-diagnostics.s
directive-tlsdescseq.s
directive-type-diagnostics.s
directive-unsupported.s
directive-word-diagnostics.s
directives-case_insensitive.s
dot-req-case-insensitive.s
dot-req.s
dwarf-asm-multiple-sections-dwarf-2.s
dwarf-asm-multiple-sections.s
dwarf-asm-no-code.s
dwarf-asm-nonstandard-section.s
dwarf-asm-single-section.s
dwarf-cfi-initial-state.s
eh-compact-pr0.s
eh-compact-pr1.s
eh-directive-cantunwind-diagnostics.s
eh-directive-cantunwind.s
eh-directive-fnend-diagnostics.s
eh-directive-fnstart-diagnostics.s
eh-directive-handlerdata.s
eh-directive-integrated-test.s
eh-directive-movsp-diagnostics.s
eh-directive-movsp.s
eh-directive-multiple-offsets.s
eh-directive-pad-diagnostics.s
eh-directive-pad.s
eh-directive-personality-diagnostics.s
eh-directive-personality.s
eh-directive-personalityindex-diagnostics.s
eh-directive-personalityindex.s
eh-directive-save-diagnostics.s
eh-directive-save.s
eh-directive-section-comdat.s
eh-directive-section-multiple-func.s
eh-directive-section.s
eh-directive-setfp-diagnostics.s
eh-directive-setfp.s
eh-directive-text-section-multiple-func.s
eh-directive-text-section.s
eh-directive-unwind_raw-diagnostics.s
eh-directive-unwind_raw.s
eh-directive-vsave-diagnostics.s
eh-directive-vsave.s
eh-link.s
ehabi-personality-abs.s
elf-eflags-eabi.s
elf-execute-only-section.ll
elf-jump24-fixup.s
elf-movt.s
elf-reloc-01.s
elf-reloc-02.s
elf-reloc-03.s
elf-reloc-condcall.s
elf-thumbfunc-reloc2.s
elf-thumbfunc-reloc.s
elf-thumbfunc.s
equal-rdhi-rdlo-diagnostics.s
error-location-ldr-pseudo.s
error-location-post-layout.s
error-location.s
fconst.s
fixup-cpu-mode.s
fixup-pcrel9.s
fixup-per-fragment.s
fp-armv8-m.s
fp-armv8.s
fp-const-errors.s
full_line_comment.s
fullfp16-neg.s
fullfp16-neon-neg.s
fullfp16-neon.s
fullfp16-nopred.s
fullfp16.s
gas-compl-copr-reg.s
gas-compl-mem-offset-paren.s
hilo-16bit-relocations.s
idiv.s
implicit-it-generation.s
implicit-it.s
inline-asm-diags.ll
inline-asm-srcloc.ll	[clang] Use i64 for the !srcloc metadata on asm IR nodes.	2021-07-22 10:24:52 +01:00
inline-comments-arm.ll
inst-arm-suffixes.s
inst-constant-required.s
inst-directive-emit.s
inst-directive-other.s
inst-directive.s
inst-overflow.s
inst-thumb-overflow-2.s
inst-thumb-overflow.s
inst-thumb-suffixes-auto.s
inst-thumb-suffixes.s
invalid-addsub.s
invalid-barrier.s
invalid-crc32.s
invalid-fp-armv8.s
invalid-hint-arm.s
invalid-hint-thumb.s
invalid-idiv.s
invalid-instructions-spellcheck.s
invalid-neon-v8.s
invalid-special-reg.s
invalid-vector-index.s
it-nv.s
ldr-pseudo-cond-darwin.s
ldr-pseudo-cond.s
ldr-pseudo-darwin.s
ldr-pseudo-obj-errors.s
ldr-pseudo-parse-errors.s
ldr-pseudo-unpredictable.s
ldr-pseudo-wide.s
ldr-pseudo.s
ldrd-strd-gnu-arm-bad-imm.s
ldrd-strd-gnu-arm-bad-regs.s
ldrd-strd-gnu-arm.s
ldrd-strd-gnu-bad-inst.s
ldrd-strd-gnu-sp.s
ldrd-strd-gnu-thumb-bad-regs.s
ldrd-strd-gnu-thumb.s
lit.local.cfg
load-store-acquire-release-v8-thumb.s
load-store-acquire-release-v8.s
lsl-zero-errors.s
lsl-zero.s
ltorg-darwin.s
ltorg-range.s
ltorg.s
macho-movwt.s
macho-reloc-thumb-local.s
macho-relocs-with-addend.s
macho-word-reloc-thumb.s
mapping-initial.s
mapping-within-section.s
mappingsymbols.s	[test] Avoid llvm-readelf/llvm-readobj one-dash long options and deprecated aliases (e.g. --file-headers)	2021-07-15 10:26:21 -07:00
misaligned-blx.s
mixed-arm-thumb-bl-fixup.ll
mode-switch.s
modified-immediate-fixup-error.s
modified-immediate-fixup.s
move-banked-regs.s
mul-v4.s
multi-section-mapping.s
mve-bitops.s
mve-float.s
mve-fp-registers.s
mve-integer.s
mve-interleave.s
mve-load-store.s
mve-minmax.s
mve-misc.s
mve-qdest-qsrc.s
mve-qdest-rsrc.s
mve-reductions-fp.s
mve-reductions.s
mve-scalar-shift.s
mve-shifts.s
mve-vcmp.s
mve-vmov-lane.s
mve-vmov-pair.s
mve-vpt.s
negative-immediates-fail.s
negative-immediates-thumb1-fail.s
negative-immediates-thumb1.s
negative-immediates.s
neon-abs-encoding.s
neon-absdiff-encoding.s
neon-add-encoding.s
neon-bitcount-encoding.s
neon-bitwise-encoding.s
neon-cmp-encoding.s
neon-complex.s
neon-convert-encoding.s
neon-crypto.s	[ARM][AArch64] Require appropriate features for crypto algorithms	2021-04-28 16:26:18 +01:00
neon-dup-encoding.s
neon-minmax-encoding.s
neon-mov-encoding.s
neon-mov-vfp.s
neon-mul-accum-encoding.s
neon-mul-encoding.s
neon-neg-encoding.s
neon-pairwise-encoding.s
neon-reciprocal-encoding.s
neon-reverse-encoding.s
neon-satshift-encoding.s
neon-shift-encoding.s
neon-shiftaccum-encoding.s
neon-shuffle-encoding.s
neon-sub-encoding.s
neon-table-encoding.s
neon-v8.s
neon-vcvt-fp16.s
neon-vld-encoding.s
neon-vld-vst-align.s
neon-vst-encoding.s
neon-vswp.s
neont2-abs-encoding.s
neont2-absdiff-encoding.s
neont2-add-encoding.s
neont2-bitcount-encoding.s
neont2-bitwise-encoding.s
neont2-cmp-encoding.s
neont2-convert-encoding.s
neont2-dup-encoding.s
neont2-minmax-encoding.s
neont2-mov-encoding.s
neont2-mul-accum-encoding.s
neont2-mul-encoding.s
neont2-neg-encoding.s
neont2-pairwise-encoding.s
neont2-reciprocal-encoding.s
neont2-reverse-encoding.s
neont2-satshift-encoding.s
neont2-shift-encoding.s
neont2-shiftaccum-encoding.s
neont2-shuffle-encoding.s
neont2-sub-encoding.s
neont2-table-encoding.s
neont2-vld-encoding.s
neont2-vst-encoding.s
no-mve.s
not-armv4.s
obsolete-v8.s
pcrel-global.s
pkhbt-archs.s
pool.s
pr11877.s
pr22395-2.s
pr22395.s
preserve-comments-arm.s
quad-relocation.s
ras-extension.s
register-list-dup.s
register-token-source-loc.s
reloc-directive-err.s
reloc-directive.s	[MC][ARM] Support .reloc *, BFD_RELOC_{NONE,8,16,32}, *	2021-03-05 21:39:16 -08:00
relocated-mapping.s
simple-fp-encoding.s
single-precision-fp.s
speculation-barriers-errors.s
speculation-barriers.s
sub-expr-imm.s
symbol-variants-errors.s
symbol-variants.s
t2-modified-immediate-fixup-error1.s
t2-modified-immediate-fixup-error2.s
t2-modified-immediate-fixup.s
target-expressions.s
thumb1-branch-reloc.s
thumb1-relax-8m-baseline.s
thumb1-relax-adr.s
thumb1-relax-bcc.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
thumb1-relax-br.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
thumb1-relax-ldrlit.s
thumb1-relax.s
thumb2-b.w-encodingT4.s
thumb2-b.w-target.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
thumb2-beq-fixup.s
thumb2-branch-ranges.s	[ARM] support symbolic expressions as branch target in b.w	2021-03-01 17:41:35 -08:00
thumb2-branches.s	[MC][ARM] add .w suffixes for BL (T1) and DBG	2021-02-24 09:58:08 -08:00
thumb2-bxj-v8.s
thumb2-bxj.s
thumb2-cbn-to-next-inst.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
thumb2-diagnostics.s	[MC][ARM] Reject Thumb "ror rX, #0"	2021-05-19 15:05:39 -07:00
thumb2-dsp-diag.s
thumb2-exception-return-mclass.s
thumb2-ldr.w-str.w.s
thumb2-ldrb-ldrh.s
thumb2-ldrd.s
thumb2-ldrexd-strexd.s
thumb2-mclass.s
thumb2-narrow-dp.ll
thumb2-pldw.s
thumb2-strd.s
thumb2be-b.w-encoding.s
thumb2be-beq.w-encoding.s
thumb2be-movt-encoding.s
thumb2be-movw-encoding.s
thumb_func-implies-thumb.s	[AsmParser][ARM] Make .thumb_func imply .thumb	2021-05-07 12:13:36 +02:00
thumb_rewrites.s
thumb_set-diagnostics.s	[MC] Add parseEOL() overload and migrate some parseToken(AsmToken::EndOfStatement) to parseEOL()	2021-03-06 17:45:23 -08:00
thumb_set.s
thumb-add-sub-width.s
thumb-branch-errors.s
thumb-branches.s
thumb-cb-offsets.s
thumb-cb-thumbfunc.s	[ARMInstPrinter] Print the target address of a branch instruction	2021-06-30 16:35:28 +07:00
thumb-diagnostics.s
thumb-far-jump.s
thumb-fp-armv8.s
thumb-function-address.s	[MC][ARM] make Thumb function also if type attribute is set	2021-02-24 14:08:56 -08:00
thumb-hints.s
thumb-invalid-crypto.txt
thumb-load-store-multiple.s
thumb-mov.s
thumb-movwt-reloc.s
thumb-neon-crypto.s
thumb-neon-v8.s
thumb-not-mclass.s
thumb-only-conditionals.s
thumb-shift-encoding.s
thumb-st_other.s
thumb-types.s
thumb.s
thumbv7em.s
thumbv7m.s
thumbv8.1m-vmrs-vmsr.s
thumbv8.1m.s
thumbv8m.s
tls-directives.s
tMOVSr.s
twice.ll
type-directive-print.ll
udf-arm-diagnostics.s
udf-arm.s
udf-thumb-2-diagnostics.s
udf-thumb-2.s
udf-thumb-diagnostics.s
udf-thumb.s
unpred-control-flow-in-it-block.s
unwind-stack-diagnostics.s
v7k-dsp.s
v8_IT_manual.s
variant-diagnostics.s
vfp4.s
vfp-aliases-diagnostics.s
vfp-aliases.s
virtexts-arm.s
virtexts-thumb.s
vldm-vstm-diags.s
vmov-pair-diags.s
vmov-vmvn-illegal-cases.s
vmov-vmvn-replicate.s
vmovhr.s
vmrs_vmsr.s
vorr-vbic-illegal-cases.s
vpush-vpop.s
vscclrm-asm.s
vstrldr_sys.s