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3d936b9a18
This adds diagnostic strings for the ARM general-purpose register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, rGPR, requires C++ code to select the correct error message, as that class contains different registers in pre-v8 and v8 targets. The rest can all have their diagnostic strings stored in the tablegen description of them. Differential revision: https://reviews.llvm.org/D36692 llvm-svn: 315303
109 lines
4.3 KiB
ArmAsm
109 lines
4.3 KiB
ArmAsm
@ New ARMv8 T32 encodings
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@ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
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@ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
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@ HLT (in ARMv8 only)
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hlt #0
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hlt #63
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@ CHECK-V8: hlt #0 @ encoding: [0x80,0xba]
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@ CHECK-V8: hlt #63 @ encoding: [0xbf,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ In IT block
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it pl
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hlt #24
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@ CHECK-V8: it pl @ encoding: [0x58,0xbf]
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ Can accept AL condition code (in ARMv8 only)
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hltal #24
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@ CHECK-V8: hlt #24 @ encoding: [0x98,0xba]
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@ CHECK-V7: error: instruction requires: armv8
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@ Can accept SP as rGPR (in ARMv8 only)
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sbc.w r6, r3, sp, asr #16
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and.w r6, r3, sp, asr #16
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and sp, r0, #0
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@ CHECK-V8: sbc.w r6, r3, sp, asr #16 @ encoding: [0x63,0xeb,0x2d,0x46]
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@ CHECK-V8: and.w r6, r3, sp, asr #16 @ encoding: [0x03,0xea,0x2d,0x46]
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@ CHECK-V8: and sp, r0, #0 @ encoding: [0x00,0xf0,0x00,0x0d]
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@ CHECK-V7: error: invalid instruction, any one of the following would fix this:
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@ CHECK-V7-NEXT: sbc.w r6, r3, sp, asr #16
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@ CHECK-V7: note: instruction variant requires ARMv8 or later
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@ CHECK-V7: note: operand must be a register in range [r0, r12] or r14
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@ CHECK-V7: error: invalid instruction, any one of the following would fix this:
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@ CHECK-V7-NEXT: and.w r6, r3, sp, asr #16
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@ CHECK-V7: note: invalid operand for instruction
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@ CHECK-V7: note: instruction variant requires ARMv8 or later
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@ CHECK-V7: note: operand must be a register in range [r0, r12] or r14
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@ CHECK-V7: error: invalid instruction, any one of the following would fix this:
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@ CHECK-V7-NEXT: and sp, r0, #0
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@ CHECK-V7: note: operand must be a register in range [r0, r12] or r14
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@ CHECK-V7: note: invalid operand for instruction
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@ DCPS{1,2,3} (in ARMv8 only)
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dcps1
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dcps2
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dcps3
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@ CHECK-V8: dcps1 @ encoding: [0x8f,0xf7,0x01,0x80]
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@ CHECK-V8: dcps2 @ encoding: [0x8f,0xf7,0x02,0x80]
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@ CHECK-V8: dcps3 @ encoding: [0x8f,0xf7,0x03,0x80]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@------------------------------------------------------------------------------
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@ DMB (ARMv8-only barriers)
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@------------------------------------------------------------------------------
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dmb ishld
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dmb oshld
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dmb nshld
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dmb ld
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@ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
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@ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
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@ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
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@ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@------------------------------------------------------------------------------
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@ DSB (ARMv8-only barriers)
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@------------------------------------------------------------------------------
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dsb ishld
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dsb oshld
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dsb nshld
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dsb ld
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@ CHECK-V8: dsb ishld @ encoding: [0xbf,0xf3,0x49,0x8f]
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@ CHECK-V8: dsb oshld @ encoding: [0xbf,0xf3,0x41,0x8f]
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@ CHECK-V8: dsb nshld @ encoding: [0xbf,0xf3,0x45,0x8f]
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@ CHECK-V8: dsb ld @ encoding: [0xbf,0xf3,0x4d,0x8f]
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@ CHECK-V7: error: invalid operand for instruction
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@------------------------------------------------------------------------------
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@ SEVL (in ARMv8 only)
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@------------------------------------------------------------------------------
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sevl
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sevl.w
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it ge
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sevlge
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@ CHECK-V8: sevl @ encoding: [0x50,0xbf]
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@ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]
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@ CHECK-V8: it ge @ encoding: [0xa8,0xbf]
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@ CHECK-V8: sevlge @ encoding: [0x50,0xbf]
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error: instruction requires: armv8
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@ CHECK-V7: error:
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@ CHECK-V7: error: instruction requires: armv8
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