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49633b5f44
Summary: This patch adds assembly-level support for a new Arm M-profile architecture extension, Custom Datapath Extension (CDE). A brief description of the extension is available at https://developer.arm.com/architectures/instruction-sets/custom-instructions The latest specification for CDE is currently a beta release and is available at https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf CDE allows chip vendors to add custom CPU instructions. The CDE instructions re-use the same encoding space as existing coprocessor instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range cp0-cp7 can be configured as either general purpose (GCP) or custom datapath (CDEv1). This configuration is defined by the CPU vendor and is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7. The semantics of CDE instructions are implementation-defined, but the instructions are guaranteed to be pure (that is, they are stateless, they do not access memory or any registers except their explicit inputs/outputs). CDE requires the CPU to support at least Armv8.0-M mainline architecture. CDE includes 3 sets of instructions: * Instructions that operate on general purpose registers and NZCV flags * Instructions that operate on the S or D register file (require either FP or MVE extension) * Instructions that operate on the Q register file, require MVE The user-facing names that can be specified on the command line are the same as the 8 subtarget feature names. For example: $ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 tells the compiler that the coprocessors 0 and 3 are configured as CDEv1 and the remaining coprocessors are configured as GCP (which is the default). Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74044
130 lines
6.2 KiB
ArmAsm
130 lines
6.2 KiB
ArmAsm
// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8 -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck %s
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// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-FP %s
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// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8d16sp -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck %s
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// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-FP %s
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// RUN: not llvm-mc -triple=thumbv8.1m.main -mattr=+mve -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck --check-prefixes=CHECK,CHECK-MVE %s
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// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-MVE %s
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// CHECK-LABEL: test_predication:
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test_predication:
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ittt eq
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
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vcx1a p1, s7, #2047
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
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vcx2 p0, d0, d15, #0
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// ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
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// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
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vcx3 p0, q0, q7, q0, #12
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nop
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nop
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nop
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// CHECK-LABEL: test_vcx1:
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test_vcx1:
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// CHECK-NEXT: vcx1 p0, s11, #1234 @ encoding: [0x69,0xec,0x92,0x50]
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vcx1 p0, s11, #1234
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// CHECK-NEXT: vcx1a p1, s7, #2047 @ encoding: [0x6f,0xfc,0xbf,0x31]
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vcx1a p1, s7, #2047
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// CHECK-NEXT: vcx1 p0, d0, #0 @ encoding: [0x20,0xed,0x00,0x00]
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vcx1 p0, d0, #0
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// CHECK-NEXT: vcx1a p1, d3, #2047 @ encoding: [0x2f,0xfd,0xbf,0x31]
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vcx1a p1, d3, #2047
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// CHECK-MVE-NEXT: vcx1 p0, q1, #1234 @ encoding: [0x29,0xec,0xd2,0x20]
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
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vcx1 p0, q1, #1234
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// CHECK-MVE-NEXT: vcx1a p1, q5, #4095 @ encoding: [0x2f,0xfd,0xff,0xa1]
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1a p1, q5, #4095
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1a p1, s7, s7, #2047
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,2047]
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vcx1 p0, d0, #2048
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,2047]
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vcx1a p1, s0, #2048
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1 p0, q0, #4096
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// ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: error: coprocessor must be in the range [p0, p7]
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// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
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vcx1 p8, d0, #1234
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1 p0, d16, #1234
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1 p0, s32, #1234
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// ERROR-FP: [[@LINE+4]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
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// ERROR-FP: [[@LINE+3]]:{{[0-9]+}}: note: operand must be a register in range [s0, s31]
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// ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]
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// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q7]
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vcx1 p0, q8, #1234
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// ERROR: [[@LINE+3]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
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// ERROR: [[@LINE+2]]:{{[0-9]+}}: note: operand must be a register in range [s0, s31]
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]
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vcx1 p0, r0, #1234
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1 p0, d0, d0, #0
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx1a p0, d0, d2, #0
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// CHECK-LABEL: test_vcx2:
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test_vcx2:
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// CHECK-NEXT: vcx2 p0, s0, s31, #12 @ encoding: [0x33,0xec,0x2f,0x00]
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vcx2 p0, s0, s31, #12
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// CHECK-NEXT: vcx2a p0, s1, s1, #63 @ encoding: [0x7f,0xfc,0xb0,0x00]
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vcx2a p0, s1, s1, #63
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// CHECK-NEXT: vcx2 p0, d0, d15, #0 @ encoding: [0x30,0xed,0x0f,0x00]
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vcx2 p0, d0, d15, #0
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// CHECK-NEXT: vcx2a p0, d1, d11, #63 @ encoding: [0x3f,0xfd,0x9b,0x10]
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vcx2a p0, d1, d11, #63
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// CHECK-MVE: vcx2 p1, q0, q6, #123 @ encoding: [0x3e,0xed,0xdc,0x01]
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vcx2 p1, q0, q6, #123
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// CHECK-MVE: vcx2a p1, q3, q7, #127 @ encoding: [0x3f,0xfd,0xde,0x61]
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vcx2a p1, q3, q7, #127
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,63]
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vcx2 p0, d0, d1, #64
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,63]
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vcx2a p0, s3, s1, #64
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// ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,127]
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx2a p0, q1, q5, #128
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d15]
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vcx2 p1, d0, q2, #0
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [s0, s31]
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vcx2a p1, q2, s3, #0
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx2 p1, d0, d0, d2, #0
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx2a p1, q2, q3, q1, #0
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// CHECK-LABEL: test_vcx3:
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test_vcx3:
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// CHECK-NEXT: vcx3 p0, s0, s31, s0, #1 @ encoding: [0x8f,0xec,0x90,0x00]
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vcx3 p0, s0, s31, s0, #1
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// CHECK-NEXT: vcx3a p1, s1, s17, s11, #7 @ encoding: [0xf8,0xfc,0xb5,0x01]
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vcx3a p1, s1, s17, s11, #7
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// CHECK-NEXT: vcx3 p0, d0, d15, d7, #0 @ encoding: [0x8f,0xed,0x07,0x00]
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vcx3 p0, d0, d15, d7, #0
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// CHECK-NEXT: vcx3a p1, d1, d11, d11, #7 @ encoding: [0xbb,0xfd,0x1b,0x11]
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vcx3a p1, d1, d11, d11, #7
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// CHECK-MVE-NEXT: vcx3 p0, q0, q2, q0, #12 @ encoding: [0xa4,0xed,0x40,0x00]
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vcx3 p0, q0, q2, q0, #12
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// CHECK-MVE-NEXT: vcx3a p1, q3, q7, q6, #15 @ encoding: [0xbe,0xfd,0x5c,0x61]
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vcx3a p1, q3, q7, q6, #15
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,7]
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vcx3a p1, d1, d11, d12, #8
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// ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,15]
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// ERROR-FP: error: invalid instruction
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vcx3a p1, q1, q2, q3, #16
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// ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
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// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d15]
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vcx3 p0, d0, q0, d7, #1
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [s0, s31]
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vcx3a p1, s0, s1, d3, #2
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx3a p0, s0, d0, q0, #2
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx3 p0, s0, s0, s31, s0, #1
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// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
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vcx3a p1, d1, d3, d22, d22, #7
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