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b87985e436
The APSR is encoded by setting bit 15 in the register list of the CLRM instruction (cf. https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf). Differential Revision: https://reviews.llvm.org/D65873 llvm-svn: 368711
32 lines
1.2 KiB
ArmAsm
32 lines
1.2 KiB
ArmAsm
// RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t \
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// RUN: | FileCheck --check-prefix=CHECK %s
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// RUN: FileCheck --check-prefix=ERROR < %t %s
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// CHECK: clrm {r0, r1, r2, r3} @ encoding: [0x9f,0xe8,0x0f,0x00]
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clrm {r0, r1, r2, r3}
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// CHECK: clrm {r1, r2, r3, r4} @ encoding: [0x9f,0xe8,0x1e,0x00]
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// ERROR-NOT: register list not in ascending order
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clrm {r3, r4, r1, r2}
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// CHECK: clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr} @ encoding: [0x9f,0xe8,0xff,0xdf]
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clrm {r0-r12, lr, apsr}
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// CHECK: clrm {lr, apsr} @ encoding: [0x9f,0xe8,0x00,0xc0]
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clrm {apsr, lr}
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// CHECK: clrm {r0, r1, apsr} @ encoding: [0x9f,0xe8,0x03,0x80]
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clrm {apsr, r1, r0}
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// CHECK: clrm {r0, r1, r2, r3, r4, lr, apsr} @ encoding: [0x9f,0xe8,0x1f,0xc0]
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clrm {r0-r4, apsr, lr}
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// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
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clrm {sp}
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// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
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clrm {r13}
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// ERROR: invalid register in register list. Valid registers are r0-r12, lr/r14 and APSR.
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clrm {r0-r12, sp}
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