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a1d7f2fdc1
Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
27 lines
974 B
ArmAsm
27 lines
974 B
ArmAsm
@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,+d32 2>&1 | FileCheck %s --check-prefix=D32
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@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,-d32 2>&1 | FileCheck %s --check-prefix=D16
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@ D32-NOT: error:
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@ D16: error: invalid instruction, any one of the following would fix this:
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@ D16-NEXT: vadd.f64 d1, d2, d16
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@ D16: note: operand must be a register in range [d0, d15]
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@ D16: note: too many operands for instruction
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vadd.f64 d1, d2, d16
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vadd.f64 d1, d17, d6
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vadd.f64 d1, d17, d6
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vadd.f64 d19, d7, d6
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vadd.f64 d19, d7, d6
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vcvt.f64.f32 d22, s4
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vcvt.f64.f32 d22, s4
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vcvt.f32.f64 s26, d30
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vcvt.f32.f64 s26, d30
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