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b7078d6c0f
This is used by the Linux kernel built with CONFIG_THUMB2_KERNEL. Because different operands are not permitted to `movs`, the diagnostics now provide multiple suggestions along the lines of using a non-pc destination operand or lr source operand. Forked from D95586. Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed By: DavidSpickett Differential Revision: https://reviews.llvm.org/D96304
160 lines
7.9 KiB
ArmAsm
160 lines
7.9 KiB
ArmAsm
// RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck --check-prefixes=CHECK-NONARM,CHECK-THUMBV7 %s
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// RUN: not llvm-mc -triple=thumbv8 -show-encoding < %s 2>&1 | FileCheck --check-prefixes=CHECK-NONARM,CHECK-THUMBV8 %s
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// RUN: llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck --check-prefix=CHECK-ARM %s
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// lsl #0 is actually mov, so here we check that it behaves the same as
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// mov with regards to the permitted registers
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// Using PC is invalid in thumb
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lsl pc, r0, #0
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lsl r0, pc, #0
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lsl pc, pc, #0
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lsls pc, r0, #0
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lsls r0, pc, #0
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lsls pc, pc, #0
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: lsl pc, r0, #0
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// CHECK-NONARM: note: instruction requires: arm-mode
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// CHECK-NONARM: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: lsl r0, pc, #0
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// CHECK-NONARM: note: instruction requires: arm-mode
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// CHECK-NONARM: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsl pc, pc, #0
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: lsls pc, r0, #0
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// CHECK-NONARM: note: instruction requires: arm-mode
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// CHECK-NONARM: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: lsls r0, pc, #0
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// CHECK-NONARM: note: instruction requires: arm-mode
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// CHECK-NONARM: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: instruction requires: arm-mode
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// CHECK-NONARM-NEXT: lsls pc, pc, #0
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// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
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// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
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// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
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// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
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// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
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// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
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mov pc, r0, lsl #0
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mov r0, pc, lsl #0
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mov pc, pc, lsl #0
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movs pc, r0, lsl #0
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movs r0, pc, lsl #0
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movs pc, pc, lsl #0
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: mov pc, r0, lsl #0
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// CHECK-NONARM: note: operand must be a register in range [r0, r15]
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: mov r0, pc, lsl #0
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// CHECK-NONARM: note: operand must be a register in range [r0, r15]
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-NONARM: note: operand must be an immediate in the range [256,65535]
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: mov pc, pc, lsl #0
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// CHECK-NONARM: note: operand must be a register in range [r0, r15]
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: movs pc, r0, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: movs r0, pc, lsl #0
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// CHECK-NONARM: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-NONARM: error: invalid instruction, any one of the following would fix this:
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// CHECK-NONARM-NEXT: movs pc, pc, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV8: note: operand must be a register in range [r0, r14]
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// CHECK-NONARM: note: invalid operand for instruction
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// CHECK-ARM: mov pc, r0 @ encoding: [0x00,0xf0,0xa0,0xe1]
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// CHECK-ARM: mov r0, pc @ encoding: [0x0f,0x00,0xa0,0xe1]
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// CHECK-ARM: mov pc, pc @ encoding: [0x0f,0xf0,0xa0,0xe1]
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// CHECK-ARM: movs pc, r0 @ encoding: [0x00,0xf0,0xb0,0xe1]
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// CHECK-ARM: movs r0, pc @ encoding: [0x0f,0x00,0xb0,0xe1]
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// CHECK-ARM: movs pc, pc @ encoding: [0x0f,0xf0,0xb0,0xe1]
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// Using SP is invalid before ARMv8 in thumb unless non-flags-setting
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// and one of the source and destination is not SP
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lsl sp, sp, #0
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lsls sp, sp, #0
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lsls r0, sp, #0
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lsls sp, r0, #0
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: lsl sp, sp, #0
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// CHECK-THUMBV7: instruction requires: arm-mode
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// CHECK-THUMBV7: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: lsls sp, sp, #0
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// CHECK-THUMBV7: instruction requires: arm-mode
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// CHECK-THUMBV7: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: lsls r0, sp, #0
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// CHECK-THUMBV7: instruction requires: arm-mode
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// CHECK-THUMBV7: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: lsls sp, r0, #0
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// CHECK-THUMBV7: instruction requires: arm-mode
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// CHECK-THUMBV7: instruction variant requires ARMv8 or later
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// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
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// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
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// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
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// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
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mov sp, sp, lsl #0
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movs sp, sp, lsl #0
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movs r0, sp, lsl #0
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movs sp, r0, lsl #0
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// FIXME: We should consistently have the "requires ARMv8" error here
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: mov sp, sp, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r15]
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: movs sp, sp, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: movs r0, sp, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]
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// CHECK-THUMBV7: note: invalid operand for instruction
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// CHECK-THUMBV7: note: instruction variant requires ARMv8 or later
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// CHECK-THUMBV7: error: invalid instruction, any one of the following would fix this:
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// CHECK-THUMBV7-NEXT: movs sp, r0, lsl #0
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r14]
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// CHECK-THUMBV7: note: operand must be a register in range [r0, r12] or r14
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// CHECK-ARM: mov sp, sp @ encoding: [0x0d,0xd0,0xa0,0xe1]
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// CHECK-ARM: movs sp, sp @ encoding: [0x0d,0xd0,0xb0,0xe1]
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// CHECK-ARM: movs r0, sp @ encoding: [0x0d,0x00,0xb0,0xe1]
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// CHECK-ARM: movs sp, r0 @ encoding: [0x00,0xd0,0xb0,0xe1]
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