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e7b30c99aa
This adds the family of loads and stores with names like VLD20.8 and VST42.32, which load and store parts of multiple q-registers in such a way that executing both VLD20 and VLD21, or all four of VLD40..VLD43, will distribute 2 or 4 vectors' worth of memory data across the lanes of the same number of registers but in a transposed order. In addition to the Tablegen descriptions of the instructions themselves, this patch also adds encode and decode support for the QQPR and QQQQPR register classes (representing the range of loaded or stored vector registers), and tweaks to the parsing system for lists of vector registers to make it return the right format in this case (since, unlike NEON, MVE regards q-registers as primitive, and not just an alias for two d-registers). llvm-svn: 364172
271 lines
9.2 KiB
ArmAsm
271 lines
9.2 KiB
ArmAsm
# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2> %t \
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# RUN: | FileCheck --check-prefix=CHECK %s
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# RUN: FileCheck --check-prefix=ERROR < %t %s
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# CHECK: vld20.8 {q0, q1}, [sp] @ encoding: [0x9d,0xfc,0x00,0x1e]
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vld20.8 {q0, q1}, [sp]
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# CHECK: vld20.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1e]
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vld20.8 {q0, q1}, [r0]
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# CHECK: vld20.8 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1e]
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vld20.8 {q0, q1}, [r0]!
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# CHECK: vld20.8 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1e]
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vld20.8 {q0, q1}, [r11]
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# CHECK: vld20.8 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbe]
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vld20.8 {q5, q6}, [r0]!
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# CHECK: vld21.8 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1e]
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vld21.8 {q0, q1}, [r0]
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# CHECK: vld21.8 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7e]
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vld21.8 {q3, q4}, [r0]!
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# CHECK: vld20.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x80,0x1e]
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vld20.16 {q0, q1}, [r0]
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# CHECK: vld20.16 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x80,0x1e]
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vld20.16 {q0, q1}, [r0]!
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# CHECK: vld20.16 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x80,0x1e]
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vld20.16 {q0, q1}, [r11]
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# CHECK: vld20.16 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x80,0xbe]
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vld20.16 {q5, q6}, [r0]!
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# CHECK: vld21.16 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0xa0,0x1e]
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vld21.16 {q0, q1}, [r0]
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# CHECK: vld21.16 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0xa0,0x7e]
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vld21.16 {q3, q4}, [r0]!
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# CHECK: vld20.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x00,0x1f]
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vld20.32 {q0, q1}, [r0]
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# CHECK: vld20.32 {q0, q1}, [r0]! @ encoding: [0xb0,0xfc,0x00,0x1f]
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vld20.32 {q0, q1}, [r0]!
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# CHECK: vld20.32 {q0, q1}, [r11] @ encoding: [0x9b,0xfc,0x00,0x1f]
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vld20.32 {q0, q1}, [r11]
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# CHECK: vld20.32 {q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x00,0xbf]
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vld20.32 {q5, q6}, [r0]!
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# CHECK: vld21.32 {q0, q1}, [r0] @ encoding: [0x90,0xfc,0x20,0x1f]
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vld21.32 {q0, q1}, [r0]
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# CHECK: vld21.32 {q3, q4}, [r0]! @ encoding: [0xb0,0xfc,0x20,0x7f]
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vld21.32 {q3, q4}, [r0]!
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# CHECK: vst20.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1e]
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vst20.8 {q0, q1}, [r0]
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# CHECK: vst20.8 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1e]
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vst20.8 {q0, q1}, [r0]!
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# CHECK: vst20.8 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1e]
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vst20.8 {q0, q1}, [r11]
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# CHECK: vst20.8 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbe]
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vst20.8 {q5, q6}, [r0]!
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# CHECK: vst21.8 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1e]
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vst21.8 {q0, q1}, [r0]
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# CHECK: vst21.8 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7e]
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vst21.8 {q3, q4}, [r0]!
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# CHECK: vst20.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x80,0x1e]
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vst20.16 {q0, q1}, [r0]
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# CHECK: vst20.16 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x80,0x1e]
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vst20.16 {q0, q1}, [r0]!
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# CHECK: vst20.16 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x80,0x1e]
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vst20.16 {q0, q1}, [r11]
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# CHECK: vst20.16 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x80,0xbe]
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vst20.16 {q5, q6}, [r0]!
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# CHECK: vst21.16 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0xa0,0x1e]
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vst21.16 {q0, q1}, [r0]
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# CHECK: vst21.16 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0xa0,0x7e]
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vst21.16 {q3, q4}, [r0]!
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# CHECK: vst20.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x00,0x1f]
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vst20.32 {q0, q1}, [r0]
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# CHECK: vst20.32 {q0, q1}, [r0]! @ encoding: [0xa0,0xfc,0x00,0x1f]
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vst20.32 {q0, q1}, [r0]!
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# CHECK: vst20.32 {q0, q1}, [r11] @ encoding: [0x8b,0xfc,0x00,0x1f]
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vst20.32 {q0, q1}, [r11]
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# CHECK: vst20.32 {q5, q6}, [r0]! @ encoding: [0xa0,0xfc,0x00,0xbf]
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vst20.32 {q5, q6}, [r0]!
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# CHECK: vst21.32 {q0, q1}, [r0] @ encoding: [0x80,0xfc,0x20,0x1f]
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vst21.32 {q0, q1}, [r0]
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# CHECK: vst21.32 {q3, q4}, [r0]! @ encoding: [0xa0,0xfc,0x20,0x7f]
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vst21.32 {q3, q4}, [r0]!
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld20.8 {q0, q1}, [sp]!
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld20.64 {q0, q1}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
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vld20.32 {q0, q2}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
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vld20.32 {q0, q1, q2}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of two consecutive q-registers in range [q0,q7]
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vld20.32 {q0}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
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vld20.32 q0, q1, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
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vld20.32 {q7, q8}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
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vld20.32 {d0, d1}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
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vld22.32 {q0, q1}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld20.32 {q0, q1}, [pc]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld20.32 {q0, q1}, [r0, #4]
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# CHECK: vld40.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1e]
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vld40.8 {q0, q1, q2, q3}, [r0]
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# CHECK: vld40.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1e]
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vld40.8 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld40.8 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1e]
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vld40.8 {q0, q1, q2, q3}, [r11]
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# CHECK: vld40.8 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7e]
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vld40.8 {q3, q4, q5, q6}, [r0]!
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# CHECK: vld41.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1e]
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vld41.8 {q0, q1, q2, q3}, [r0]
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# CHECK: vld41.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9e]
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vld41.8 {q4, q5, q6, q7}, [r0]!
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# CHECK: vld42.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1e]
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vld42.8 {q0, q1, q2, q3}, [r0]
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# CHECK: vld42.8 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1e]
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vld42.8 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld43.8 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1e]
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vld43.8 {q0, q1, q2, q3}, [r0]
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# CHECK: vld43.8 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9e]
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vld43.8 {q4, q5, q6, q7}, [r0]!
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# CHECK: vld40.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x81,0x1e]
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vld40.16 {q0, q1, q2, q3}, [r0]
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# CHECK: vld40.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x1e]
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vld40.16 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld40.16 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x81,0x1e]
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vld40.16 {q0, q1, q2, q3}, [r11]
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# CHECK: vld40.16 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x81,0x7e]
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vld40.16 {q3, q4, q5, q6}, [r0]!
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# CHECK: vld41.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xa1,0x1e]
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vld41.16 {q0, q1, q2, q3}, [r0]
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# CHECK: vld41.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xa1,0x9e]
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vld41.16 {q4, q5, q6, q7}, [r0]!
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# CHECK: vld42.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xc1,0x1e]
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vld42.16 {q0, q1, q2, q3}, [r0]
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# CHECK: vld42.16 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0xc1,0x1e]
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vld42.16 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld43.16 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0xe1,0x1e]
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vld43.16 {q0, q1, q2, q3}, [r0]
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# CHECK: vld43.16 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0xe1,0x9e]
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vld43.16 {q4, q5, q6, q7}, [r0]!
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# CHECK: vld40.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x01,0x1f]
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vld40.32 {q0, q1, q2, q3}, [r0]
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# CHECK: vld40.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x1f]
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vld40.32 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld40.32 {q0, q1, q2, q3}, [r11] @ encoding: [0x9b,0xfc,0x01,0x1f]
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vld40.32 {q0, q1, q2, q3}, [r11]
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# CHECK: vld40.32 {q3, q4, q5, q6}, [r0]! @ encoding: [0xb0,0xfc,0x01,0x7f]
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vld40.32 {q3, q4, q5, q6}, [r0]!
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# CHECK: vld41.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x21,0x1f]
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vld41.32 {q0, q1, q2, q3}, [r0]
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# CHECK: vld41.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x21,0x9f]
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vld41.32 {q4, q5, q6, q7}, [r0]!
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# CHECK: vld42.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x41,0x1f]
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vld42.32 {q0, q1, q2, q3}, [r0]
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# CHECK: vld42.32 {q0, q1, q2, q3}, [r0]! @ encoding: [0xb0,0xfc,0x41,0x1f]
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vld42.32 {q0, q1, q2, q3}, [r0]!
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# CHECK: vld43.32 {q0, q1, q2, q3}, [r0] @ encoding: [0x90,0xfc,0x61,0x1f]
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vld43.32 {q0, q1, q2, q3}, [r0]
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# CHECK: vld43.32 {q4, q5, q6, q7}, [r0]! @ encoding: [0xb0,0xfc,0x61,0x9f]
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vld43.32 {q4, q5, q6, q7}, [r0]!
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld40.64 {q0, q1, q2, q3}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: non-contiguous register range
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vld40.32 {q0, q2, q3, q4}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
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vld40.32 {q0, q1, q2, q3, q4}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
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vld40.32 {q0, q1}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a list of four consecutive q-registers in range [q0,q7]
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vld40.32 {q0, q1, q2}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
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vld40.32 q0, q1, q2, q3, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
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vld40.32 {q5, q6, q7, q8}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: vector register in range Q0-Q7 expected
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vld40.32 {d0, d1, d2, d3}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid instruction
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vld44.32 {q0, q1, q2, q3}, [r0]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld40.32 {q0, q1, q2, q3}, [pc]
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# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
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vld40.32 {q0, q1, q2, q3}, [r0, #4]
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