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bc0266a9ee
This includes all the obvious bitwise operations (AND, OR, BIC, ORN, MVN) in register-to-register forms, and the immediate forms of AND/OR/BIC/ORN; byte-order reverse instructions; and the VMOVs that access a single lane of a vector. Some of those VMOVs (specifically, the ones that access a 32-bit lane) share an encoding with existing instructions that were disassembled as accessing half of a d-register (e.g. `vmov.32 r0, d1[0]`), but in 8.1-M they're now written as accessing a quarter of a q-register (e.g. `vmov.32 r0, q0[2]`). The older syntax is still accepted by the assembler. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62673 llvm-svn: 363838
17 lines
915 B
ArmAsm
17 lines
915 B
ArmAsm
// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8 -show-encoding < %s 2>%t | FileCheck %s --check-prefix=V80M
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// RUN: FileCheck %s < %t --check-prefix=V80M-ERROR
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// RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+fp-armv8 -show-encoding < %s 2>%t
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// RUN: llvm-mc -triple=thumbv8.1m.main -mattr=+mve -show-encoding < %s 2>%t
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// v8.1M added the Q register syntax for this instruction. The v8.1M spec does
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// not list the D register syntax as valid, but we accept it as an extension to
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// make porting code from v8.0M to v8.1M easier.
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vmov.32 r0, d1[0]
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// V80M: vmov.32 r0, d1[0] @ encoding: [0x11,0xee,0x10,0x0b]
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// V81M: vmov.32 r0, d1[0] @ encoding: [0x11,0xee,0x10,0x0b]
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vmov.32 r0, q0[2]
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// V80M-ERROR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction requires: armv8.1m.main with FP or MVE
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// V81M: vmov.32 r0, q0[2] @ encoding: [0x11,0xee,0x10,0x0b]
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