Craig Topper 1f378948f5 [RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL. ... All that really matters is that the VLMAX of the preceding instructions is the same as the VLMAX required by the mask operation. Also update the vmsge(u) handling to use the SEW/LMUL we use for other mask register operations. We were matching it to the compare before. Some cases will be improve if we fix masked compares to use tail agnostic policy. I think they ignore the tail policy anyway. Reviewed By: frasercrmck Differential Revision: https://reviews.llvm.org/D103299		2021-06-04 09:17:46 -07:00
..
AsmParser	RISCV: add a few deprecated aliases for CSRs	2021-05-21 13:52:58 -07:00
Disassembler
MCTargetDesc	Revert "[RISCV] Remove -riscv-no-aliases in favour of new -M no-aliases"	2021-05-29 15:11:37 +01:00
TargetInfo
CMakeLists.txt	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.h	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCV.td
RISCVAsmPrinter.cpp	[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.	2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp
RISCVExpandPseudoInsts.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVFrameLowering.h
RISCVInsertVSETVLI.cpp	[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.	2021-06-04 09:17:46 -07:00
RISCVInstrFormats.td	[RISCV] Cleanup instruction formats used for B extension ternary operations.	2021-05-06 08:59:05 -07:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td
RISCVInstrInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVInstrInfo.h	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVInstrInfo.td	[RISCV] Replace AddiPair ComplexPattern with a PatLeaf. NFC	2021-05-16 12:17:52 -07:00
RISCVInstrInfoA.td
RISCVInstrInfoB.td	[RISCV] Optimize xor/or with immediate in the zbs extension	2021-05-25 14:14:09 +08:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td	[RISCV] Cleanup instruction formats used for B extension ternary operations.	2021-05-06 08:59:05 -07:00
RISCVInstrInfoF.td	[RISCV] Cleanup instruction formats used for B extension ternary operations.	2021-05-06 08:59:05 -07:00
RISCVInstrInfoM.td
RISCVInstrInfoV.td
RISCVInstrInfoVPseudos.td	[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.	2021-06-04 09:17:46 -07:00
RISCVInstrInfoVSDPatterns.td	[RISCV] Minor vector instruction tablegen cleanup. NFC	2021-05-06 11:23:59 -07:00
RISCVInstrInfoVVLPatterns.td	[RISCV] Add octuple to LMULInfo tablegen class, remove octuple_from_str. NFCI	2021-05-28 11:53:05 -07:00
RISCVInstrInfoZfh.td	[RISCV] Cleanup instruction formats used for B extension ternary operations.	2021-05-06 08:59:05 -07:00
RISCVInstructionSelector.cpp
RISCVISelDAGToDAG.cpp	[RISCV] Teach vsetvli insertion pass that operations on masks don't care about SEW/LMUL.	2021-06-04 09:17:46 -07:00
RISCVISelDAGToDAG.h	[RISCV] Optimize SEW=64 shifts by splat on RV32.	2021-05-26 10:23:32 -07:00
RISCVISelLowering.cpp	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00
RISCVISelLowering.h	[RISCV] Support vector types in combination with fastcc	2021-06-01 10:31:18 +01:00
RISCVLegalizerInfo.cpp	[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one	2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp	[RISCV] Move instruction information into the RISCVII namespace (NFC)	2021-05-11 16:32:42 -05:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp	[RISCV] Reserve an emergency spill slot for any RVV spills	2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSchedRocket.td
RISCVSchedSiFive7.td
RISCVSchedule.td
RISCVScheduleB.td
RISCVSubtarget.cpp
RISCVSubtarget.h	[RISCV] Enable interleaved vectorization for RVV	2021-05-29 11:03:27 +08:00
RISCVSystemOperands.td	RISCV: add a few deprecated aliases for CSRs	2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp	[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.	2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp	[RISCV] Add support for fmin/fmax vector reductions	2021-05-03 10:33:51 +01:00
RISCVTargetTransformInfo.h	[RISCV] Expand unaligned fixed-length vector memory accesses	2021-06-02 09:27:44 +01:00