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llvm-mirror/test/MC/Mips/mips64r5
Daniel Sanders 556791680d [mips][ias] Range check uimm5 operands and fix several bugs this revealed.
Summary:
The bugs were:
* append, prepend, and balign were not tested
* balign takes a uimm2 not a uimm5.
* drotr32 was correctly implemented with a uimm5 but the tests expected
  '52' to be valid.
* li/la were implemented with a uimm5 instead of simm32. simm32 isn't
  completely correct either but I'll fix that when I get to simm32.

A notable omission are some of the shift instructions. Several of these
have been implemented using a single uimm6 instruction (rather than two
uimm5 instructions and a CodeGen-only uimm6 pseudo). These will be updated
in the uimm6 patch.

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D14712

llvm-svn: 254164
2015-11-26 16:35:41 +00:00
..
abi-bad.s
abiflags.s
invalid-mips64.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid-mips64r2.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid-mips64r3.s [mips] Added support for the ERETNC instruction. 2015-07-20 12:28:56 +00:00
invalid.s [mips][ias] Range check uimm5 operands and fix several bugs this revealed. 2015-11-26 16:35:41 +00:00
valid-xfail.s
valid.s [mips] Added support for various EVA ASE instructions. 2015-09-15 10:02:16 +00:00