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4e2f16caa6
The second register is the index register and should only be %si or %di if used with a base register. And in that case the base register should be %bp or %bx. This makes us compatible with gas. We do still need to support both orders with Intel syntax which uses [bp+si] and [si+bp] llvm-svn: 335384
30 lines
834 B
ArmAsm
30 lines
834 B
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
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.code64
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movb $0x0, (%esi)
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// CHECK: encoding: [0x67,0xc6,0x06,0x00]
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movb $0x0, (%rsi)
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// CHECK: encoding: [0xc6,0x06,0x00]
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.code32
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movb $0x0, (%si)
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// CHECK: encoding: [0x67,0xc6,0x04,0x00]
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movb $0x0, (%esi)
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// CHECK: encoding: [0xc6,0x06,0x00]
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movw $0x1234, (%si)
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// CHECK: encoding: [0x67,0x66,0xc7,0x04,0x34,0x12]
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movl $0x12345678, (%bx,%si,1)
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// CHECK: encoding: [0x67,0xc7,0x00,0x78,0x56,0x34,0x12]
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movw $0x1234, 0x5678(%bp)
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// CHECK: encoding: [0x67,0x66,0xc7,0x86,0x78,0x56,0x34,0x12]
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.code16
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movb $0x0, (%si)
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// CHECK: encoding: [0xc6,0x04,0x00]
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movb $0x0, (%esi)
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// CHECK: encoding: [0x67,0xc6,0x06,0x00]
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movb $0x5a, (%bp,%di,1)
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// CHECK: encoding: [0xc6,0x03,0x5a]
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movb $0x5a, (%bp,%si,1)
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// CHECK: encoding: [0xc6,0x02,0x5a]
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