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46cdf3f128
Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
157 lines
3.0 KiB
YAML
157 lines
3.0 KiB
YAML
# RUN: llc -run-pass x86-fixup-bw-insts -mtriple=x86_64-- -o - %s | FileCheck %s
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# Verify that we correctly deal with the flag edge cases when replacing
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# copies by bigger copies, which is a pretty unusual transform.
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--- |
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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define i8 @test_movb_killed(i8 %a0) {
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ret i8 %a0
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}
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define i8 @test_movb_impuse(i8 %a0) {
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ret i8 %a0
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}
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define i8 @test_movb_impdef_gr64(i8 %a0) {
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ret i8 %a0
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}
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define i8 @test_movb_impdef_gr32(i8 %a0) {
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ret i8 %a0
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}
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define i8 @test_movb_impdef_gr16(i8 %a0) {
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ret i8 %a0
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}
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define i16 @test_movw_impdef_gr32(i16 %a0) {
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ret i16 %a0
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}
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define i16 @test_movw_impdef_gr64(i16 %a0) {
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ret i16 %a0
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}
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...
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---
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name: test_movb_killed
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %dil
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%al = MOV8rr killed %dil
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RETQ killed %al
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...
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---
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name: test_movb_impuse
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %dil
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%al = MOV8rr %dil, implicit %edi
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RETQ killed %al
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...
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---
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name: test_movb_impdef_gr64
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
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%al = MOV8rr %dil, implicit-def %rax
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RETQ killed %al
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...
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---
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name: test_movb_impdef_gr32
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %dil
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%al = MOV8rr %dil, implicit-def %eax
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RETQ killed %al
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...
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---
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name: test_movb_impdef_gr16
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %dil
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%al = MOV8rr %dil, implicit-def %ax
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RETQ killed %al
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...
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---
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name: test_movw_impdef_gr32
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %di
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%ax = MOV16rr %di, implicit-def %eax
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RETQ killed %ax
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...
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---
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name: test_movw_impdef_gr64
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allVRegsAllocated: true
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isSSA: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%edi' }
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body: |
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bb.0 (%ir-block.0):
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liveins: %edi
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; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
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%ax = MOV16rr %di, implicit-def %rax
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RETQ killed %ax
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...
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