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llvm-mirror/test/CodeGen/NVPTX
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Jingyue Wu 2b97db6061 [MachineSink] Use the real post dominator tree 
Summary:
Fixes a FIXME in MachineSinking. Instead of using the simple heuristics
in isPostDominatedBy, use the real MachinePostDominatorTree. The old
heuristics caused instructions to sink unnecessarily, and might create
register pressure.

Test Plan:
Added a NVPTX codegen test to verify that our change is in effect. It also
shows the unnecessary register pressure caused by over-sinking. Updated
affected tests in AArch64 and X86.

Reviewers: eliben, meheff, Jiangning

Reviewed By: Jiangning

Subscribers: jholewinski, aemerson, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D4814

llvm-svn: 216862
2014-09-01 03:47:25 +00:00
..
access-non-generic.ll Canonicalize addrspacecast ConstExpr between different pointer types 2014-06-15 21:40:57 +00:00
add-128bit.ll
addrspacecast-gvar.ll [NVPTX] Add support for addrspacecast in global variable initializers, including emitting generic() when casting to address space 0. 2014-04-09 15:39:11 +00:00
addrspacecast.ll Optimize away unnecessary address casts. 2014-04-03 21:18:25 +00:00
aggr-param.ll
annotations.ll
arg-lowering.ll [NVPTX] Clean up argument lowering code and properly handle alignment for structs and vectors 2014-06-27 18:35:44 +00:00
arithmetic-fp-sm20.ll [NVPTX] Improve handling of FP fusion 2014-07-17 18:10:09 +00:00
arithmetic-int.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
atomics.ll Add some tests for NVPTX lowering of cmpxchg 2014-07-21 22:54:44 +00:00
bfe.ll [NVPTX] Add isel patterns for bit-field extract (bfe) 2014-06-27 18:35:27 +00:00
bug17709.ll
call-with-alloca-buffer.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
callchain.ll
calling-conv.ll
compare-int.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
constant-vectors.ll
convert-fp.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
convert-int-sm20.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
ctlz.ll
ctpop.ll
cttz.ll
div-ri.ll
envreg.ll [NVPTX] Add support for envreg reads 2014-06-27 18:35:21 +00:00
fast-math.ll
fma-disable.ll
fma.ll [NVPTX] Improve handling of FP fusion 2014-07-17 18:10:09 +00:00
fp16.ll NVPTX: support direct f16 <-> f64 conversions via intrinsics. 2014-07-18 08:30:10 +00:00
fp-contract.ll [NVPTX] Improve handling of FP fusion 2014-07-17 18:10:09 +00:00
fp-literals.ll [NVPTX] Improve handling of FP fusion 2014-07-17 18:10:09 +00:00
generic-to-nvvm.ll
global-ordering.ll
gvar-init.ll [NVPTX] Error out if initializer is given for variable in an address space that does not support initialization 2014-06-27 18:36:01 +00:00
half.ll NVPTX: support fpext/fptrunc to and from f16. 2014-07-18 13:01:43 +00:00
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll
imad.ll [NVPTX] Implement fma and imad contraction as target DAGCombiner patterns 2014-06-27 18:35:37 +00:00
implicit-def.ll [NVPTX] Improve handling of FP fusion 2014-07-17 18:10:09 +00:00
inline-asm.ll [NVPTX] Add 'b' asm constraint 2014-06-27 18:36:06 +00:00
intrin-nocapture.ll
intrinsic-old.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
intrinsics.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
isspacep.ll [NVPTX] Add support for isspacep instruction 2014-06-27 18:35:24 +00:00
ld-addrspace.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
ld-generic.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
ldparam-v4.ll
ldu-i8.ll [NVPTX] Make the alignment an explicit argument to ldu/ldg 2014-08-29 15:30:20 +00:00
ldu-ldg.ll [NVPTX] Make the alignment an explicit argument to ldu/ldg 2014-08-29 15:30:20 +00:00
ldu-reg-plus-offset.ll [NVPTX] Make the alignment an explicit argument to ldu/ldg 2014-08-29 15:30:20 +00:00
lit.local.cfg Reduce verbiage of lit.local.cfg files 2014-06-09 22:42:55 +00:00
load-sext-i1.ll
local-stack-frame.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
machine-sink.ll [MachineSink] Use the real post dominator tree 2014-09-01 03:47:25 +00:00
managed.ll [NVPTX] Add support for .managed variables for UVM 2014-06-27 18:35:58 +00:00
misaligned-vector-ldst.ll [NVPTX] Honor alignment on vector loads/stores 2014-07-16 19:45:35 +00:00
module-inline-asm.ll
mulwide.ll [NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types 2014-07-23 20:23:49 +00:00
noduplicate-syncthreads.ll Expose "noduplicate" attribute as a property for intrinsics. 2014-03-18 23:51:07 +00:00
nvvm-reflect.ll [NVPTX] Add reflect intrinsic (better than matching by function name) 2014-06-27 18:36:11 +00:00
param-align.ll
pr13291-i1-store.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
pr16278.ll
pr17529.ll
ptx-version-30.ll
ptx-version-31.ll
refl1.ll
rotate.ll [NVPTX] Add support for efficient rotate instructions on SM 3.2+ 2014-06-27 18:35:33 +00:00
rsqrt.ll
sched1.ll
sched2.ll
sext-in-reg.ll
sext-params.ll
shift-parts.ll [NVPTX] Add support for [SHL,SRA,SRL]_PARTS 2014-06-27 18:35:40 +00:00
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-35.ll
st-addrspace.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
st-generic.ll [NVPTX] Rename registers %fl -> %fd and %rl -> %rd 2014-07-16 16:26:58 +00:00
surf-read-cuda.ll [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch 2014-07-17 11:59:04 +00:00
surf-read.ll [NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces 2014-04-09 15:39:15 +00:00
surf-write-cuda.ll [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch 2014-07-17 11:59:04 +00:00
surf-write.ll [NVPTX] Add preliminary intrinsics and codegen support for textures/surfaces 2014-04-09 15:39:15 +00:00
symbol-naming.ll Fix for PR19099 - NVPTX produces invalid symbol names. 2014-03-31 15:56:26 +00:00
tex-read-cuda.ll [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch 2014-07-17 11:59:04 +00:00
tex-read.ll [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch 2014-07-17 11:59:04 +00:00
texsurf-queries.ll [NVPTX] Flag surface/texture query instructions with IsTexSurfQuery 2014-07-17 14:51:33 +00:00
tuple-literal.ll
vec8.ll
vec-param-load.ll
vector-args.ll
vector-call.ll [NVPTX] Add missing .v4 qualifier on vector store instruction 2014-07-17 16:58:56 +00:00
vector-compare.ll
vector-loads.ll
vector-select.ll
vector-stores.ll
weak-global.ll [NVPTX] Emit .weak linkage for link_once, weak, available_externally, and common linkage 2014-06-27 18:35:56 +00:00
weak-linkage.ll [NVPTX] Emit .weak when linkage is not external, internal, or private 2014-06-27 18:35:10 +00:00