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https://github.com/RPCS3/llvm-mirror.git
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2b3fd0441a
This patch added generation of SIMD bitwise insert BIT/BIF instructions. In the absence of GCC-like functionality for optimal constraints satisfaction during register allocation the bitwise insert and select patterns are matched by pseudo bitwise select BSP instruction with not tied def. It is expanded later after register allocation with def tied to BSL/BIT/BIF depending on operands registers. This allows to get rid of redundant moves. Reviewers: t.p.northover, samparker, dmgreen Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D74147
147 lines
4.3 KiB
LLVM
147 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; BIT Bitwise Insert if True
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;
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; 8-bit vectors tests
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define <1 x i8> @test_bit_v1i8(<1 x i8> %A, <1 x i8> %B, <1 x i8> %C) {
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; CHECK-LABEL: test_bit_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <1 x i8> %C, %B
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%neg = xor <1 x i8> %C, <i8 -1>
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%and1 = and <1 x i8> %neg, %A
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%or = or <1 x i8> %and, %and1
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ret <1 x i8> %or
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}
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; 16-bit vectors tests
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define <1 x i16> @test_bit_v1i16(<1 x i16> %A, <1 x i16> %B, <1 x i16> %C) {
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; CHECK-LABEL: test_bit_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <1 x i16> %C, %B
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%neg = xor <1 x i16> %C, <i16 -1>
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%and1 = and <1 x i16> %neg, %A
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%or = or <1 x i16> %and, %and1
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ret <1 x i16> %or
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}
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; 32-bit vectors tests
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define <1 x i32> @test_bit_v1i32(<1 x i32> %A, <1 x i32> %B, <1 x i32> %C) {
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; CHECK-LABEL: test_bit_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <1 x i32> %C, %B
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%neg = xor <1 x i32> %C, <i32 -1>
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%and1 = and <1 x i32> %neg, %A
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%or = or <1 x i32> %and, %and1
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ret <1 x i32> %or
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}
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; 64-bit vectors tests
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define <1 x i64> @test_bit_v1i64(<1 x i64> %A, <1 x i64> %B, <1 x i64> %C) {
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; CHECK-LABEL: test_bit_v1i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <1 x i64> %C, %B
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%neg = xor <1 x i64> %C, <i64 -1>
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%and1 = and <1 x i64> %neg, %A
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%or = or <1 x i64> %and, %and1
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ret <1 x i64> %or
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}
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define <2 x i32> @test_bit_v2i32(<2 x i32> %A, <2 x i32> %B, <2 x i32> %C) {
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; CHECK-LABEL: test_bit_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <2 x i32> %C, %B
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%neg = xor <2 x i32> %C, <i32 -1, i32 -1>
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%and1 = and <2 x i32> %neg, %A
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%or = or <2 x i32> %and, %and1
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ret <2 x i32> %or
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}
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define <4 x i16> @test_bit_v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> %C) {
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; CHECK-LABEL: test_bit_v4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <4 x i16> %C, %B
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%neg = xor <4 x i16> %C, <i16 -1, i16 -1, i16 -1, i16 -1>
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%and1 = and <4 x i16> %neg, %A
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%or = or <4 x i16> %and, %and1
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ret <4 x i16> %or
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}
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define <8 x i8> @test_bit_v8i8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
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; CHECK-LABEL: test_bit_v8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%and = and <8 x i8> %C, %B
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%neg = xor <8 x i8> %C, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%and1 = and <8 x i8> %neg, %A
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%or = or <8 x i8> %and, %and1
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ret <8 x i8> %or
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}
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; 128-bit vectors tests
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define <2 x i64> @test_bit_v2i64(<2 x i64> %A, <2 x i64> %B, <2 x i64> %C) {
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; CHECK-LABEL: test_bit_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%and = and <2 x i64> %C, %B
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%neg = xor <2 x i64> %C, <i64 -1, i64 -1>
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%and1 = and <2 x i64> %neg, %A
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%or = or <2 x i64> %and, %and1
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ret <2 x i64> %or
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}
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define <4 x i32> @test_bit_v4i32(<4 x i32> %A, <4 x i32> %B, <4 x i32> %C) {
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; CHECK-LABEL: test_bit_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%and = and <4 x i32> %C, %B
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%neg = xor <4 x i32> %C, <i32 -1, i32 -1, i32 -1, i32 -1>
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%and1 = and <4 x i32> %neg, %A
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%or = or <4 x i32> %and, %and1
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ret <4 x i32> %or
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}
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define <8 x i16> @test_bit_v8i16(<8 x i16> %A, <8 x i16> %B, <8 x i16> %C) {
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; CHECK-LABEL: test_bit_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%and = and <8 x i16> %C, %B
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%neg = xor <8 x i16> %C, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
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%and1 = and <8 x i16> %neg, %A
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%or = or <8 x i16> %and, %and1
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ret <8 x i16> %or
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}
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define <16 x i8> @test_bit_v16i8(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C) {
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; CHECK-LABEL: test_bit_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bit v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%and = and <16 x i8> %C, %B
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%neg = xor <16 x i8> %C, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
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%and1 = and <16 x i8> %neg, %A
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%or = or <16 x i8> %and, %and1
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ret <16 x i8> %or
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}
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