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63df72fb38
This patch adds code to recognize vector shuffles which can be
represented as VDUP (splat) of a vector lane with of a different
(wider) type than the original vector lane type.
For example:
shufflevector <4 x i16> %v, <4 x i16> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
is essentially:
shufflevector <2 x i32> %v, <2 x i32> undef, <2 x i32> <i32 0, i32 0>
Such patterns are generated by the SelectionDAG machinery in some cases
(see DAGCombiner::visitBITCAST in DAGCombiner.cpp, the "Remove double
bitcasts from shuffles" part).
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D86225
173 lines
5.4 KiB
LLVM
173 lines
5.4 KiB
LLVM
; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
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; The following tests is to check the correctness of reversing input operand
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; of vext by enumerating all cases of using two undefs in shuffle masks.
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define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_0:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #4
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_12:
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; CHECK: dup v0.2s, v0.s[0]
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_13:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #4
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_14:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #4
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_23:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #4
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_24:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #4
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_6701_34:
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; CHECK: dup v0.2s, v1.s[1]
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_0:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_12:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_13:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_14:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_23:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_24:
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; CHECK: rev32 v0.4h, v1.4h
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_5670_34:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #2
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_0:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_12:
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; CHECK: ext v0.8b, v0.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_13:
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; CHECK: rev32 v0.4h, v0.4h
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_14:
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; CHECK: ext v0.8b, v0.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_23:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_24:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
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ret <4 x i16> %x
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}
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define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
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entry:
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; CHECK-LABEL: vext_7012_34:
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; CHECK: ext v0.8b, v1.8b, v0.8b, #6
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%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
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ret <4 x i16> %x
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}
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