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f2c842c94a
Follow the same strategy used for atomic loads/stores by converting the operands to equally-sized integer types. This change prevents the atomic expansion pass from generating illegal LL/SC pairs when targeting AArch64: `expand-atomicrmw-xchg-fp.ll` would previously instantiate intrinsics such as `llvm.aarch64.ldaxr.p0f32` that cannot be lowered. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D103232
113 lines
3.8 KiB
LLVM
113 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -O1 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=NOLSE
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; RUN: llc -verify-machineinstrs -mtriple=aarch64-- -mattr=+lse -O1 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s -check-prefix=LSE
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define half @test_rmw_xchg_f16(half* %dst, half %new) {
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; NOLSE-LABEL: test_rmw_xchg_f16:
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; NOLSE: // %bb.0:
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; NOLSE-NEXT: // kill: def $h0 killed $h0 def $s0
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; NOLSE-NEXT: fmov w8, s0
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; NOLSE-NEXT: .LBB0_1: // %atomicrmw.start
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; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1
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; NOLSE-NEXT: ldaxrh w9, [x0]
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; NOLSE-NEXT: stlxrh w10, w8, [x0]
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; NOLSE-NEXT: cbnz w10, .LBB0_1
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; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
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; NOLSE-NEXT: fmov s0, w9
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; NOLSE-NEXT: // kill: def $h0 killed $h0 killed $s0
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; NOLSE-NEXT: ret
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;
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; LSE-LABEL: test_rmw_xchg_f16:
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; LSE: // %bb.0:
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; LSE-NEXT: // kill: def $h0 killed $h0 def $s0
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; LSE-NEXT: fmov w8, s0
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; LSE-NEXT: swpalh w8, w8, [x0]
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; LSE-NEXT: fmov s0, w8
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; LSE-NEXT: // kill: def $h0 killed $h0 killed $s0
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; LSE-NEXT: ret
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%res = atomicrmw xchg half* %dst, half %new seq_cst
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ret half %res
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}
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define float @test_rmw_xchg_f32(float* %dst, float %new) {
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; NOLSE-LABEL: test_rmw_xchg_f32:
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; NOLSE: // %bb.0:
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; NOLSE-NEXT: fmov w9, s0
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; NOLSE-NEXT: .LBB1_1: // %atomicrmw.start
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; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1
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; NOLSE-NEXT: ldaxr w8, [x0]
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; NOLSE-NEXT: stlxr w10, w9, [x0]
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; NOLSE-NEXT: cbnz w10, .LBB1_1
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; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
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; NOLSE-NEXT: fmov s0, w8
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; NOLSE-NEXT: ret
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;
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; LSE-LABEL: test_rmw_xchg_f32:
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; LSE: // %bb.0:
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; LSE-NEXT: fmov w8, s0
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; LSE-NEXT: swpal w8, w8, [x0]
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; LSE-NEXT: fmov s0, w8
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; LSE-NEXT: ret
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%res = atomicrmw xchg float* %dst, float %new seq_cst
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ret float %res
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}
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define double @test_rmw_xchg_f64(double* %dst, double %new) {
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; NOLSE-LABEL: test_rmw_xchg_f64:
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; NOLSE: // %bb.0:
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; NOLSE-NEXT: fmov x8, d0
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; NOLSE-NEXT: .LBB2_1: // %atomicrmw.start
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; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1
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; NOLSE-NEXT: ldaxr x9, [x0]
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; NOLSE-NEXT: stlxr w10, x8, [x0]
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; NOLSE-NEXT: cbnz w10, .LBB2_1
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; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
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; NOLSE-NEXT: fmov d0, x9
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; NOLSE-NEXT: ret
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;
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; LSE-LABEL: test_rmw_xchg_f64:
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; LSE: // %bb.0:
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; LSE-NEXT: fmov x8, d0
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; LSE-NEXT: swpal x8, x8, [x0]
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; LSE-NEXT: fmov d0, x8
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; LSE-NEXT: ret
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%res = atomicrmw xchg double* %dst, double %new seq_cst
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ret double %res
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}
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define fp128 @test_rmw_xchg_f128(fp128* %dst, fp128 %new) {
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; NOLSE-LABEL: test_rmw_xchg_f128:
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; NOLSE: // %bb.0:
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; NOLSE-NEXT: sub sp, sp, #32 // =32
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; NOLSE-NEXT: .cfi_def_cfa_offset 32
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; NOLSE-NEXT: str q0, [sp, #16]
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; NOLSE-NEXT: ldp x9, x8, [sp, #16]
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; NOLSE-NEXT: .LBB3_1: // %atomicrmw.start
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; NOLSE-NEXT: // =>This Inner Loop Header: Depth=1
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; NOLSE-NEXT: ldaxp x11, x10, [x0]
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; NOLSE-NEXT: stlxp w12, x9, x8, [x0]
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; NOLSE-NEXT: cbnz w12, .LBB3_1
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; NOLSE-NEXT: // %bb.2: // %atomicrmw.end
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; NOLSE-NEXT: stp x11, x10, [sp]
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; NOLSE-NEXT: ldr q0, [sp], #32
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; NOLSE-NEXT: ret
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;
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; LSE-LABEL: test_rmw_xchg_f128:
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; LSE: // %bb.0:
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; LSE-NEXT: sub sp, sp, #32 // =32
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; LSE-NEXT: .cfi_def_cfa_offset 32
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; LSE-NEXT: str q0, [sp, #16]
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; LSE-NEXT: ldp x9, x8, [sp, #16]
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; LSE-NEXT: .LBB3_1: // %atomicrmw.start
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; LSE-NEXT: // =>This Inner Loop Header: Depth=1
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; LSE-NEXT: ldaxp x11, x10, [x0]
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; LSE-NEXT: stlxp w12, x9, x8, [x0]
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; LSE-NEXT: cbnz w12, .LBB3_1
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; LSE-NEXT: // %bb.2: // %atomicrmw.end
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; LSE-NEXT: stp x11, x10, [sp]
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; LSE-NEXT: ldr q0, [sp], #32
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; LSE-NEXT: ret
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%res = atomicrmw xchg fp128* %dst, fp128 %new seq_cst
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ret fp128 %res
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}
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