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af0734bc33
Before this instruction supported output values, it fit fairly naturally as a terminator. However, being a terminator while also supporting outputs causes some trouble, as the physreg->vreg COPY operations cannot be in the same block. Modeling it as a non-terminator allows it to be handled the same way as invoke is handled already. Most of the changes here were created by auditing all the existing users of MachineBasicBlock::isEHPad() and MachineBasicBlock::hasEHPadSuccessor(), and adding calls to isInlineAsmBrIndirectTarget or mayHaveInlineAsmBr, as appropriate. Reviewed By: nickdesaulniers, void Differential Revision: https://reviews.llvm.org/D79794
64 lines
1.5 KiB
LLVM
64 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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@X = common local_unnamed_addr global i32 0, align 4
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define i32 @test1() {
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; CHECK-LABEL: test1:
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; CHECK: .word b
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; CHECK-NEXT: .word .Ltmp0
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; CHECK: // %bb.1:
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; CHECK: .Ltmp0:
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; CHECK: .LBB0_2: // %indirect
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entry:
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callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "X"(i8* blockaddress(@test1, %indirect))
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to label %cleanup [label %indirect]
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indirect:
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br label %cleanup
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cleanup:
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%retval.0 = phi i32 [ 1, %indirect ], [ 0, %entry ]
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ret i32 %retval.0
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}
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define void @test2() {
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; CHECK-LABEL: test2:
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entry:
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%0 = load i32, i32* @X, align 4
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%and = and i32 %0, 1
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%tobool = icmp eq i32 %and, 0
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br i1 %tobool, label %if.end10, label %if.then
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if.then:
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; CHECK: .word b
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; CHECK-NEXT: .word .Ltmp2
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; CHECK: .Ltmp2:
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; CHECK-NEXT: .LBB1_3: // %if.end6
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callbr void asm sideeffect "1:\0A\09.word b, ${0:l}\0A\09", "X"(i8* blockaddress(@test2, %if.end6))
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to label %if.then4 [label %if.end6]
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if.then4:
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%call5 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
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br label %if.end6
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if.end6:
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%.pre = load i32, i32* @X, align 4
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%.pre13 = and i32 %.pre, 1
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%phitmp = icmp eq i32 %.pre13, 0
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br i1 %phitmp, label %if.end10, label %if.then9
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if.then9:
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; CHECK: .Ltmp4:
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; CHECK-NEXT: .LBB1_5: // %l_yes
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callbr void asm sideeffect "", "X"(i8* blockaddress(@test2, %l_yes))
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to label %if.end10 [label %l_yes]
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if.end10:
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br label %l_yes
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l_yes:
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ret void
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}
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declare i32 @g(...)
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