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be7f6a09b0
This is a late backend subset of the IR transform added with: D52439 We can confirm that the conversion to a 'trunc' is correct by running: $ opt -instcombine -data-layout="e" (assuming the IR transforms are correct; change "e" to "E" for big-endian) As discussed in PR39016: https://bugs.llvm.org/show_bug.cgi?id=39016 ...the pattern may emerge during legalization, so that's we are waiting for an insertelement to become a scalar_to_vector in the pattern matching here. The DAG allows for fun variations that are not possible in IR. Result types for extracts and scalar_to_vector don't necessarily match input types, so that means we have to be a bit more careful in the transform (see code comments). The tests show that we don't handle cases that require a shift (as we did in the IR version). I've left that as a potential follow-up because I'm not sure if that's a real concern at this late stage. Differential Revision: https://reviews.llvm.org/D53201 llvm-svn: 344872
127 lines
3.4 KiB
LLVM
127 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64_be-- < %s | FileCheck %s --check-prefix=BE
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; RUN: llc -mtriple=aarch64-- < %s | FileCheck %s --check-prefix=LE
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define i32 @trunc_i64_to_i32_le(i64 %x) {
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; BE-LABEL: trunc_i64_to_i32_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.4s, v0.4s
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; BE-NEXT: fmov w0, s0
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i32_le:
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; LE: // %bb.0:
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; LE-NEXT: // kill: def $w0 killed $w0 killed $x0
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <4 x i32>
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%ext = extractelement <4 x i32> %bc, i32 0
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ret i32 %ext
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}
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define i32 @trunc_i64_to_i32_be(i64 %x) {
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; BE-LABEL: trunc_i64_to_i32_be:
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; BE: // %bb.0:
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; BE-NEXT: // kill: def $w0 killed $w0 killed $x0
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i32_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: mov w0, v0.s[1]
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <4 x i32>
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%ext = extractelement <4 x i32> %bc, i32 1
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ret i32 %ext
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}
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define i16 @trunc_i64_to_i16_le(i64 %x) {
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; BE-LABEL: trunc_i64_to_i16_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov d0, x0
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; BE-NEXT: rev64 v0.8h, v0.8h
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; BE-NEXT: umov w0, v0.h[0]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i16_le:
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; LE: // %bb.0:
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; LE-NEXT: // kill: def $w0 killed $w0 killed $x0
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%ext = extractelement <8 x i16> %bc, i32 0
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ret i16 %ext
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}
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define i16 @trunc_i64_to_i16_be(i64 %x) {
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; BE-LABEL: trunc_i64_to_i16_be:
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; BE: // %bb.0:
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; BE-NEXT: // kill: def $w0 killed $w0 killed $x0
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i16_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: umov w0, v0.h[3]
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; LE-NEXT: ret
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%ins = insertelement <2 x i64> undef, i64 %x, i32 0
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%bc = bitcast <2 x i64> %ins to <8 x i16>
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%ext = extractelement <8 x i16> %bc, i32 3
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ret i16 %ext
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}
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define i8 @trunc_i32_to_i8_le(i32 %x) {
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; BE-LABEL: trunc_i32_to_i8_le:
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; BE: // %bb.0:
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; BE-NEXT: fmov s0, w0
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; BE-NEXT: rev32 v0.16b, v0.16b
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; BE-NEXT: umov w0, v0.b[0]
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i32_to_i8_le:
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; LE: // %bb.0:
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; LE-NEXT: ret
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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%bc = bitcast <4 x i32> %ins to <16 x i8>
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%ext = extractelement <16 x i8> %bc, i32 0
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ret i8 %ext
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}
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define i8 @trunc_i32_to_i8_be(i32 %x) {
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; BE-LABEL: trunc_i32_to_i8_be:
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; BE: // %bb.0:
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i32_to_i8_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov s0, w0
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; LE-NEXT: umov w0, v0.b[3]
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; LE-NEXT: ret
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%ins = insertelement <4 x i32> undef, i32 %x, i32 0
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%bc = bitcast <4 x i32> %ins to <16 x i8>
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%ext = extractelement <16 x i8> %bc, i32 3
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ret i8 %ext
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}
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; Weird type (non-power-of-2 vector) is ok.
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define i8 @trunc_i64_to_i8_be(i64 %x) {
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; BE-LABEL: trunc_i64_to_i8_be:
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; BE: // %bb.0:
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; BE-NEXT: // kill: def $w0 killed $w0 killed $x0
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; BE-NEXT: ret
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;
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; LE-LABEL: trunc_i64_to_i8_be:
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; LE: // %bb.0:
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; LE-NEXT: fmov d0, x0
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; LE-NEXT: umov w0, v0.b[7]
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; LE-NEXT: ret
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%ins = insertelement <3 x i64> undef, i64 %x, i32 0
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%bc = bitcast <3 x i64> %ins to <24 x i8>
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%ext = extractelement <24 x i8> %bc, i32 7
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ret i8 %ext
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}
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