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llvm-mirror/test/CodeGen/AArch64/fast-isel-branch-cond-mask.ll
Matthias Braun aee5f0fc5d Relax fast register allocator related test cases; NFC
- Relex hard coded registers and stack frame sizes
- Some test cleanups
- Change phi-dbg.ll to match on mir output after phi elimination instead
  of going through the whole codegen pipeline.

This is in preparation for https://reviews.llvm.org/D52010
I'm committing all the test changes upfront that work before and after
independently.

llvm-svn: 345532
2018-10-29 20:10:42 +00:00

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508 B
LLVM

; RUN: llc -mtriple=aarch64-apple-darwin -O0 -fast-isel -fast-isel-abort=0 -verify-machineinstrs < %s | FileCheck %s
define void @test(i64 %a, i64 %b, i2* %c) {
; CHECK-LABEL: test
; CHECK: and [[REG1:w[0-9]+]], {{w[0-9]+}}, #0x3
; CHECK-NEXT: strb [[REG1]], {{\[}}x2{{\]}}
; CHECK-NEXT: tbz {{w[0-9]+}}, #0,
%1 = trunc i64 %a to i2
%2 = trunc i64 %b to i1
; Force fast-isel to fall back to SDAG.
store i2 %1, i2* %c, align 8
br i1 %2, label %bb1, label %bb2
bb1:
ret void
bb2:
ret void
}