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7dcf1654f8
Based ontop of D104598, which is a NFCI-ish refactoring. Here, a restriction, that only empty blocks can be merged, is lifted. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D104597
210 lines
5.6 KiB
LLVM
210 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
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define i64 @test_or(i32 %a, i32 %b) {
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; CHECK-LABEL: test_or:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbnz w8, LBB0_2
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; CHECK-NEXT: LBB0_1: ; %common.ret
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB0_2: ; %bb1.cond.split
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbz w1, LBB0_1
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; CHECK-NEXT: ; %bb.3: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = or i1 %0, %1
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br i1 %or.cond, label %bb3, label %bb4, !prof !0
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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define i64 @test_or_select(i32 %a, i32 %b) {
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; CHECK-LABEL: test_or_select:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbnz w8, LBB1_2
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; CHECK-NEXT: LBB1_1: ; %common.ret
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB1_2: ; %bb1.cond.split
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbz w1, LBB1_1
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; CHECK-NEXT: ; %bb.3: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = select i1 %0, i1 true, i1 %1
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br i1 %or.cond, label %bb3, label %bb4, !prof !0
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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define i64 @test_and(i32 %a, i32 %b) {
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; CHECK-LABEL: test_and:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbnz w8, LBB2_2
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; CHECK-NEXT: LBB2_1: ; %common.ret
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB2_2: ; %bb1.cond.split
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbz w1, LBB2_1
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; CHECK-NEXT: ; %bb.3: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = and i1 %0, %1
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br i1 %or.cond, label %bb4, label %bb3, !prof !1
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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define i64 @test_and_select(i32 %a, i32 %b) {
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; CHECK-LABEL: test_and_select:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbnz w8, LBB3_2
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; CHECK-NEXT: LBB3_1: ; %common.ret
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; CHECK-NEXT: ret
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; CHECK-NEXT: LBB3_2: ; %bb1.cond.split
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: cbz w1, LBB3_1
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; CHECK-NEXT: ; %bb.3: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = select i1 %0, i1 %1, i1 false
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br i1 %or.cond, label %bb4, label %bb3, !prof !1
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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; If the branch is unpredictable, don't add another branch.
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define i64 @test_or_unpredictable(i32 %a, i32 %b) {
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; CHECK-LABEL: test_or_unpredictable:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: cmp w0, #0 ; =0
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: cmp w1, #0 ; =0
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; CHECK-NEXT: cset w9, eq
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: tbnz w8, #0, LBB4_2
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; CHECK-NEXT: ; %bb.1: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: LBB4_2: ; %common.ret
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp eq i32 %a, 0
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%1 = icmp eq i32 %b, 0
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%or.cond = or i1 %0, %1
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br i1 %or.cond, label %bb3, label %bb4, !unpredictable !2
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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define i64 @test_and_unpredictable(i32 %a, i32 %b) {
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; CHECK-LABEL: test_and_unpredictable:
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; CHECK: ; %bb.0: ; %bb1
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; CHECK-NEXT: cmp w0, #0 ; =0
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; CHECK-NEXT: cset w8, ne
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; CHECK-NEXT: cmp w1, #0 ; =0
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; CHECK-NEXT: cset w9, ne
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; CHECK-NEXT: and w8, w8, w9
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; CHECK-NEXT: mov x0, xzr
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; CHECK-NEXT: tbz w8, #0, LBB5_2
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; CHECK-NEXT: ; %bb.1: ; %bb4
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; CHECK-NEXT: stp x29, x30, [sp, #-16]! ; 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w30, -8
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; CHECK-NEXT: .cfi_offset w29, -16
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: ldp x29, x30, [sp], #16 ; 16-byte Folded Reload
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; CHECK-NEXT: LBB5_2: ; %common.ret
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; CHECK-NEXT: ret
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bb1:
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%0 = icmp ne i32 %a, 0
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%1 = icmp ne i32 %b, 0
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%or.cond = and i1 %0, %1
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br i1 %or.cond, label %bb4, label %bb3, !unpredictable !2
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bb3:
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ret i64 0
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bb4:
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%2 = call i64 @bar()
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ret i64 %2
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}
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declare i64 @bar()
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!0 = !{!"branch_weights", i32 5128, i32 32}
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!1 = !{!"branch_weights", i32 1024, i32 4136}
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!2 = !{}
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