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2476ae717e
This patch optimizes ISD::LRINT and ISD::LLRINT to frintx plus fcvtzs. It currently only handles the scalar version. Reviewed By: SjoerdMeijer, mstorsjo Differential Revision: https://reviews.llvm.org/D62018 llvm-svn: 361877
65 lines
1.5 KiB
LLVM
65 lines
1.5 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
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; CHECK-LABEL: testmsws:
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; CHECK: frintx [[REG:s[0-9]]], s0
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; CHECK-NEXT: fcvtzs x0, [[REG]]
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; CHECK: ret
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define i32 @testmsws(float %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxs:
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; CHECK: frintx [[REG:s[0-9]]], s0
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; CHECK-NEXT: fcvtzs x0, [[REG]]
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; CHECK-NEXT: ret
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define i64 @testmsxs(float %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f32(float %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswd:
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; CHECK: frintx [[REG:d[0-9]]], d0
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; CHECK-NEXT: fcvtzs x0, [[REG]]
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; CHECK: ret
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define i32 @testmswd(double %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsxd:
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; CHECK: frintx [[REG:d[0-9]]], d0
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; CHECK-NEXT: fcvtzs x0, [[REG]]
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; CHECK-nEXT: ret
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define i64 @testmsxd(double %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f64(double %x)
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ret i64 %0
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}
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; CHECK-LABEL: testmswl:
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; CHECK: bl llrintl
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define i32 @testmswl(fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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; CHECK-LABEL: testmsll:
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; CHECK: b llrintl
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define i64 @testmsll(fp128 %x) {
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entry:
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%0 = tail call i64 @llvm.llrint.f128(fp128 %x)
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ret i64 %0
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}
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declare i64 @llvm.llrint.f32(float) nounwind readnone
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declare i64 @llvm.llrint.f64(double) nounwind readnone
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declare i64 @llvm.llrint.f128(fp128) nounwind readnone
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