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e1e1463f1c
PAC/BTI-related codegen in the AArch64 backend is controlled by a set of LLVM IR function attributes, added to the function by Clang, based on command-line options and GCC-style function attributes. However, functions, generated in the LLVM middle end (for example, asan.module.ctor or __llvm_gcov_write_out) do not get any attributes and the backend incorrectly does not do any PAC/BTI code generation. This patch record the default state of PAC/BTI codegen in a set of LLVM IR module-level attributes, based on command-line options: * "sign-return-address", with non-zero value means generate code to sign return addresses (PAC-RET), zero value means disable PAC-RET. * "sign-return-address-all", with non-zero value means enable PAC-RET for all functions, zero value means enable PAC-RET only for functions, which spill LR. * "sign-return-address-with-bkey", with non-zero value means use B-key for signing, zero value mean use A-key. This set of attributes are always added for AArch64 targets (as opposed, for example, to interpreting a missing attribute as having a value 0) in order to be able to check for conflicts when combining module attributed during LTO. Module-level attributes are overridden by function level attributes. All the decision making about whether to not to generate PAC and/or BTI code is factored out into AArch64FunctionInfo, there shouldn't be any places left, other than AArch64FunctionInfo, which directly examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which is/will-be handled by a separate patch. Differential Revision: https://reviews.llvm.org/D85649
23 lines
598 B
LLVM
23 lines
598 B
LLVM
; RUN: llc -mtriple aarch64--none-eabi < %s | FileCheck %s
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; The BTI instruction cannot be outlined, because it needs to be the very first
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; instruction executed after an indirect call.
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@g = hidden global i32 0, align 4
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define hidden void @foo() minsize "branch-target-enforcement"="true" {
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entry:
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; CHECK: hint #34
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; CHECK: b OUTLINED_FUNCTION_0
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store volatile i32 1, i32* @g, align 4
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ret void
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}
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define hidden void @bar() minsize "branch-target-enforcement"="true" {
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entry:
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; CHECK: hint #34
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; CHECK: b OUTLINED_FUNCTION_0
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store volatile i32 1, i32* @g, align 4
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ret void
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}
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