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c41e03ba29
This adds simple patterns for signed and unsigned saturating extract narrow instructions. They combine a min/max/truncate into a single instruction, providing that the immediates on the min/max are correct for the saturation type. This is just handled in tablegen with some extra patterns. v2i64->v2i32 is not handled here as the min/max nodes are not legal, making the lowering quite different. Differential Revision: https://reviews.llvm.org/D103263
143 lines
5.9 KiB
LLVM
143 lines
5.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s
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define <4 x i16> @vqmovni32_smaxmin(<4 x i32> %s0) {
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; CHECK-LABEL: vqmovni32_smaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <4 x i32> %s0, <i32 32767, i32 32767, i32 32767, i32 32767>
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%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
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%c2 = icmp sgt <4 x i32> %s1, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
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%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
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%t = trunc <4 x i32> %s2 to <4 x i16>
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ret <4 x i16> %t
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}
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define <4 x i16> @vqmovni32_sminmax(<4 x i32> %s0) {
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; CHECK-LABEL: vqmovni32_sminmax:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <4 x i32> %s0, <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
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%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>
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%c2 = icmp slt <4 x i32> %s1, <i32 32767, i32 32767, i32 32767, i32 32767>
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%s2 = select <4 x i1> %c2, <4 x i32> %s1, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>
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%t = trunc <4 x i32> %s2 to <4 x i16>
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ret <4 x i16> %t
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}
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define <4 x i16> @vqmovni32_umaxmin(<4 x i32> %s0) {
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; CHECK-LABEL: vqmovni32_umaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp ult <4 x i32> %s0, <i32 65535, i32 65535, i32 65535, i32 65535>
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%s1 = select <4 x i1> %c1, <4 x i32> %s0, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>
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%t = trunc <4 x i32> %s1 to <4 x i16>
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ret <4 x i16> %t
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}
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define <8 x i8> @vqmovni16_smaxmin(<8 x i16> %s0) {
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; CHECK-LABEL: vqmovni16_smaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <8 x i16> %s0, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
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%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
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%c2 = icmp sgt <8 x i16> %s1, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
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%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
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%t = trunc <8 x i16> %s2 to <8 x i8>
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ret <8 x i8> %t
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}
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define <8 x i8> @vqmovni16_sminmax(<8 x i16> %s0) {
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; CHECK-LABEL: vqmovni16_sminmax:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <8 x i16> %s0, <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
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%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>
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%c2 = icmp slt <8 x i16> %s1, <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
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%s2 = select <8 x i1> %c2, <8 x i16> %s1, <8 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>
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%t = trunc <8 x i16> %s2 to <8 x i8>
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ret <8 x i8> %t
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}
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define <8 x i8> @vqmovni16_umaxmin(<8 x i16> %s0) {
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; CHECK-LABEL: vqmovni16_umaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: uqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp ult <8 x i16> %s0, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%s1 = select <8 x i1> %c1, <8 x i16> %s0, <8 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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%t = trunc <8 x i16> %s1 to <8 x i8>
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ret <8 x i8> %t
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}
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define <2 x i32> @vqmovni64_smaxmin(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_smaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, #2147483647
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: mov x9, #-2147483648
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; CHECK-NEXT: cmgt v2.2d, v1.2d, v0.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: dup v1.2d, x9
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; CHECK-NEXT: cmgt v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp slt <2 x i64> %s0, <i64 2147483647, i64 2147483647>
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%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 2147483647, i64 2147483647>
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%c2 = icmp sgt <2 x i64> %s1, <i64 -2147483648, i64 -2147483648>
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%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 -2147483648, i64 -2147483648>
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%t = trunc <2 x i64> %s2 to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @vqmovni64_sminmax(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_sminmax:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov x8, #-2147483648
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; CHECK-NEXT: dup v1.2d, x8
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; CHECK-NEXT: mov w9, #2147483647
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; CHECK-NEXT: cmgt v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: dup v1.2d, x9
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; CHECK-NEXT: cmgt v2.2d, v1.2d, v0.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp sgt <2 x i64> %s0, <i64 -2147483648, i64 -2147483648>
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%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 -2147483648, i64 -2147483648>
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%c2 = icmp slt <2 x i64> %s1, <i64 2147483647, i64 2147483647>
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%s2 = select <2 x i1> %c2, <2 x i64> %s1, <2 x i64> <i64 2147483647, i64 2147483647>
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%t = trunc <2 x i64> %s2 to <2 x i32>
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ret <2 x i32> %t
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}
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define <2 x i32> @vqmovni64_umaxmin(<2 x i64> %s0) {
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; CHECK-LABEL: vqmovni64_umaxmin:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
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; CHECK-NEXT: cmhi v1.2d, v1.2d, v0.2d
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: orn v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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entry:
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%c1 = icmp ult <2 x i64> %s0, <i64 4294967295, i64 4294967295>
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%s1 = select <2 x i1> %c1, <2 x i64> %s0, <2 x i64> <i64 4294967295, i64 4294967295>
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%t = trunc <2 x i64> %s1 to <2 x i32>
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ret <2 x i32> %t
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}
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