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18 lines
883 B
LLVM
18 lines
883 B
LLVM
; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Currently there is no custom lowering for vector shuffles operating on types
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; bigger than NEON. However, having no support opens us up to a code generator
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; hang when expanding BUILD_VECTOR. Here we just validate the promblematic case
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; successfully exits code generation.
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define void @hang_when_merging_stores_after_legalisation(<8 x i32>* %a, <2 x i32> %b) #0 {
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; CHECK-LABEL: hang_when_merging_stores_after_legalisation:
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%splat = shufflevector <2 x i32> %b, <2 x i32> undef, <8 x i32> zeroinitializer
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%interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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store <8 x i32> %interleaved.vec, <8 x i32>* %a, align 4
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ret void
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}
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attributes #0 = { nounwind "target-features"="+sve" }
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