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86e5cb5706
Specifically, this allow us to rely on the lane zero'ing behaviour of SVE reduce instructions. Co-authored-by: Paul Walker <paul.walker@arm.com> Differential Revision: https://reviews.llvm.org/D101369
240 lines
11 KiB
LLVM
240 lines
11 KiB
LLVM
; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 16 x i8> @andv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: andv_zero_fill:
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; CHECK: andv b0, p0, z0.b
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; CHECK-NEXT: ret
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%t1 = call i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)
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%t2 = insertelement <vscale x 16 x i8> zeroinitializer, i8 %t1, i64 0
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ret <vscale x 16 x i8> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 8 x i16> @eorv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: eorv_zero_fill:
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; CHECK: eorv h0, p0, z0.h
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; CHECK-NEXT: ret
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%t1 = call i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a)
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%t2 = insertelement <vscale x 8 x i16> zeroinitializer, i16 %t1, i64 0
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ret <vscale x 8 x i16> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x double> @fadda_zero_fill(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a) #0 {
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; CHECK-LABEL: fadda_zero_fill:
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; CHECK: fadda d0, p0, d0, z1.d
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; CHECK-NEXT: ret
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%t1 = call double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1> %pg, double %init, <vscale x 2 x double> %a)
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%t2 = insertelement <vscale x 2 x double> zeroinitializer, double %t1, i64 0
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ret <vscale x 2 x double> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 4 x float> @faddv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a) #0 {
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; CHECK-LABEL: faddv_zero_fill:
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; CHECK: faddv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a)
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%t2 = insertelement <vscale x 4 x float> zeroinitializer, float %t1, i64 0
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ret <vscale x 4 x float> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 8 x half> @fmaxv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a) #0 {
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; CHECK-LABEL: fmaxv_zero_fill:
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; CHECK: fmaxv h0, p0, z0.h
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; CHECK-NEXT: ret
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%t1 = call half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1> %pg, <vscale x 8 x half> %a)
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%t2 = insertelement <vscale x 8 x half> zeroinitializer, half %t1, i64 0
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ret <vscale x 8 x half> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x float> @fmaxnmv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {
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; CHECK-LABEL: fmaxnmv_zero_fill:
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; CHECK: fmaxnmv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call float @llvm.aarch64.sve.fmaxnmv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)
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%t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 0
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ret <vscale x 2 x float> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x float> @fminnmv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {
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; CHECK-LABEL: fminnmv_zero_fill:
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; CHECK: fminnmv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call float @llvm.aarch64.sve.fminnmv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)
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%t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 0
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ret <vscale x 2 x float> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x float> @fminv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a) #0 {
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; CHECK-LABEL: fminv_zero_fill:
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; CHECK: fminv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call float @llvm.aarch64.sve.fminv.nxv2f32(<vscale x 2 x i1> %pg, <vscale x 2 x float> %a)
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%t2 = insertelement <vscale x 2 x float> zeroinitializer, float %t1, i64 0
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ret <vscale x 2 x float> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 4 x i32> @orv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: orv_zero_fill:
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; CHECK: orv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a)
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%t2 = insertelement <vscale x 4 x i32> zeroinitializer, i32 %t1, i64 0
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ret <vscale x 4 x i32> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x i64> @saddv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: saddv_zero_fill:
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; CHECK: saddv d0, p0, z0.b
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; CHECK-NEXT: ret
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%t1 = call i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)
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%t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0
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ret <vscale x 2 x i64> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x i64> @smaxv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: smaxv_zero_fill:
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; CHECK: smaxv d0, p0, z0.d
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; CHECK-NEXT: ret
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%t1 = call i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
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%t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0
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ret <vscale x 2 x i64> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 4 x i32> @sminv_zero_fill(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: sminv_zero_fill:
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; CHECK: sminv s0, p0, z0.s
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; CHECK-NEXT: ret
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%t1 = call i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a)
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%t2 = insertelement <vscale x 4 x i32> zeroinitializer, i32 %t1, i64 0
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ret <vscale x 4 x i32> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x i64> @uaddv_zero_fill(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) #0 {
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; CHECK-LABEL: uaddv_zero_fill:
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; CHECK: uaddv d0, p0, z0.h
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; CHECK-NEXT: ret
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%t1 = call i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a)
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%t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0
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ret <vscale x 2 x i64> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 16 x i8> @umaxv_zero_fill(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: umaxv_zero_fill:
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; CHECK: umaxv b0, p0, z0.b
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; CHECK-NEXT: ret
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%t1 = call i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a)
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%t2 = insertelement <vscale x 16 x i8> zeroinitializer, i8 %t1, i64 0
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ret <vscale x 16 x i8> %t2
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}
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; Ensure we rely on the reduction's implicit zero filling.
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define <vscale x 2 x i64> @uminv_zero_fill(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: uminv_zero_fill:
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; CHECK: uminv d0, p0, z0.d
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; CHECK-NEXT: ret
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%t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
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%t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 0
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ret <vscale x 2 x i64> %t2
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}
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; Ensure explicit zeroing when inserting into a lane other than 0.
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; NOTE: This test doesn't care about the exact way an insert is code generated,
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; so only checks the presence of one instruction from the expected chain.
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define <vscale x 2 x i64> @zero_fill_non_zero_index(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: zero_fill_non_zero_index:
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; CHECK: uminv d{{[0-9]+}}, p0, z0.d
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; CHECK: mov z{{[0-9]+}}.d, p{{[0-9]+}}/m, x{{[0-9]+}}
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; CHECK: ret
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%t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
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%t2 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t1, i64 1
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ret <vscale x 2 x i64> %t2
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}
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; Ensure explicit zeroing when the result vector is larger than that produced by
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; the reduction instruction.
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define <vscale x 4 x i64> @zero_fill_type_mismatch(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: zero_fill_type_mismatch:
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; CHECK: uminv d0, p0, z0.d
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; CHECK-NEXT: mov z1.d, #0
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; CHECK-NEXT: ret
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%t1 = call i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a)
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%t2 = insertelement <vscale x 4 x i64> zeroinitializer, i64 %t1, i64 0
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ret <vscale x 4 x i64> %t2
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}
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; Ensure explicit zeroing when extracting an element from an operation that
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; cannot guarantee lanes 1-N are zero.
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; NOTE: This test doesn't care about the exact way an insert is code generated,
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; so only checks the presence of one instruction from the expected chain.
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define <vscale x 2 x i64> @zero_fill_no_zero_upper_lanes(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) #0 {
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; CHECK-LABEL: zero_fill_no_zero_upper_lanes:
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; CHECK: umin z{{[0-9]+}}.d, p0/m, z0.d, z0.d
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; CHECK: mov z{{[0-9]+}}.d, p{{[0-9]+}}/m, x{{[0-9]+}}
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; CHECK: ret
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%t1 = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.nxv2i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %a)
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%t2 = extractelement <vscale x 2 x i64> %t1, i64 0
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%t3 = insertelement <vscale x 2 x i64> zeroinitializer, i64 %t2, i64 0
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ret <vscale x 2 x i64> %t3
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}
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declare i8 @llvm.aarch64.sve.andv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i8 @llvm.aarch64.sve.andv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
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declare i8 @llvm.aarch64.sve.eorv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i16 @llvm.aarch64.sve.eorv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
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declare float @llvm.aarch64.sve.fadda.nxv2f32(<vscale x 2 x i1>, float, <vscale x 2 x float>)
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declare double @llvm.aarch64.sve.fadda.nxv2f64(<vscale x 2 x i1>, double, <vscale x 2 x double>)
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declare float @llvm.aarch64.sve.faddv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)
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declare float @llvm.aarch64.sve.faddv.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>)
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declare float @llvm.aarch64.sve.fmaxnmv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)
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declare half @llvm.aarch64.sve.fmaxv.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>)
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declare float @llvm.aarch64.sve.fmaxv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)
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declare float @llvm.aarch64.sve.fminv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)
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declare float @llvm.aarch64.sve.fminnmv.nxv2f32(<vscale x 2 x i1>, <vscale x 2 x float>)
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declare i8 @llvm.aarch64.sve.orv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i32 @llvm.aarch64.sve.orv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)
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declare i64 @llvm.aarch64.sve.saddv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i64 @llvm.aarch64.sve.saddv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
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declare i8 @llvm.aarch64.sve.smaxv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i64 @llvm.aarch64.sve.smaxv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
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declare i8 @llvm.aarch64.sve.sminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i32 @llvm.aarch64.sve.sminv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>)
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declare i64 @llvm.aarch64.sve.uaddv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i64 @llvm.aarch64.sve.uaddv.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>)
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declare i8 @llvm.aarch64.sve.umaxv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i8 @llvm.aarch64.sve.umaxv.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>)
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declare i8 @llvm.aarch64.sve.uminv.nxv2i8(<vscale x 2 x i1>, <vscale x 2 x i8>)
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declare i64 @llvm.aarch64.sve.uminv.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.umin.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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attributes #0 = { "target-features"="+sve" }
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