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c91415a58a
At the intrinsic layer the sve.insr operation takes a scalar. When this scalar is an integer we are forcing a data transition between GPRs and ZPRs that is potentially costly. Often the integer scalar is the result of a vector extract, when performing a reduction for example. In such cases we should keep all data within the ZPRs. Co-authored-by: Paul Walker <paul.walker@arm.com> Differential Revision: https://reviews.llvm.org/D101169
50 lines
2.1 KiB
LLVM
50 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
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define <vscale x 16 x i8> @insr_zpr_only_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: insr_zpr_only_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: insr z0.b, b1
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; CHECK-NEXT: ret
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%t0 = extractelement <vscale x 16 x i8> %b, i64 0
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%t1 = tail call <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8> %a, i8 %t0)
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ret <vscale x 16 x i8> %t1
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}
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define <vscale x 8 x i16> @insr_zpr_only_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
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; CHECK-LABEL: insr_zpr_only_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: insr z0.h, h1
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; CHECK-NEXT: ret
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%t0 = extractelement <vscale x 8 x i16> %b, i64 0
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%t1 = tail call <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16> %a, i16 %t0)
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ret <vscale x 8 x i16> %t1
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}
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define <vscale x 4 x i32> @insr_zpr_only_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
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; CHECK-LABEL: insr_zpr_only_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: insr z0.s, s1
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; CHECK-NEXT: ret
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%t0 = extractelement <vscale x 4 x i32> %b, i64 0
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%t1 = tail call <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32> %a, i32 %t0)
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ret <vscale x 4 x i32> %t1
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}
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define <vscale x 2 x i64> @insr_zpr_only_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: insr_zpr_only_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: insr z0.d, d1
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; CHECK-NEXT: ret
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%t0 = extractelement <vscale x 2 x i64> %b, i64 0
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%t1 = tail call <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64> %a, i64 %t0)
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ret <vscale x 2 x i64> %t1
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.insr.nxv16i8(<vscale x 16 x i8>, i8)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.insr.nxv8i16(<vscale x 8 x i16>, i16)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.insr.nxv4i32(<vscale x 4 x i32>, i32)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.insr.nxv2i64(<vscale x 2 x i64>, i64)
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attributes #0 = { "target-features"="+sve" }
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