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efaaa8cb7c
This can be done only with moves which theoretically will optimize better later. Although this transform increases the instruction count, it should be code size / cycle count neutral in the worst VALU case. It also seems to slightly improve a couple of testcases due to other DAG combines this exposes. This is probably slightly worse for the SALU case, so it might be better to handle this during moveToVALU, although then you lose some simplifications like the load width reducing in the simple testcase. llvm-svn: 242177
213 lines
8.7 KiB
LLVM
213 lines
8.7 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
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; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -check-prefix=VI %s
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declare i32 @llvm.r600.read.tidig.x() #0
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;EG: {{^}}shl_v2i32:
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI: {{^}}shl_v2i32:
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: {{^}}shl_v2i32:
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = shl <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;EG: {{^}}shl_v4i32:
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI: {{^}}shl_v4i32:
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: {{^}}shl_v4i32:
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = shl <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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;EG: {{^}}shl_i64:
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;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
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;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
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;EG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
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;EG_CHECK-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]]
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;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]}}, {{[[OVERF]]|PV.[XYZW]}}
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;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]}}
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;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
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;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
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;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
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;SI: {{^}}shl_i64:
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI: {{^}}shl_i64:
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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%a = load i64, i64 addrspace(1) * %in
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%b = load i64, i64 addrspace(1) * %b_ptr
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%result = shl i64 %a, %b
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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;EG: {{^}}shl_v2i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: LSHL {{.*}}, [[SHA]]
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;EG-DAG: LSHL {{.*}}, [[SHB]]
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;EG-DAG: LSHL {{.*}}, [[SHA]]
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;EG-DAG: LSHL {{.*}}, [[SHB]]
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;EG-DAG: LSHL
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;EG-DAG: LSHL
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;SI: {{^}}shl_v2i64:
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI: {{^}}shl_v2i64:
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
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%a = load <2 x i64>, <2 x i64> addrspace(1) * %in
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%b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
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%result = shl <2 x i64> %a, %b
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store <2 x i64> %result, <2 x i64> addrspace(1)* %out
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ret void
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}
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;EG: {{^}}shl_v4i64:
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
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;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHA]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHB]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHC]]
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;EG-DAG: LSHR {{\*? *}}[[COMPSHD]]
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: LSHR {{.*}}, 1
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
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;EG-DAG: LSHL {{.*}}, [[SHA]]
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;EG-DAG: LSHL {{.*}}, [[SHB]]
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;EG-DAG: LSHL {{.*}}, [[SHC]]
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;EG-DAG: LSHL {{.*}}, [[SHD]]
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;EG-DAG: LSHL {{.*}}, [[SHA]]
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;EG-DAG: LSHL {{.*}}, [[SHB]]
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;EG-DAG: LSHL {{.*}}, [[SHC]]
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;EG-DAG: LSHL {{.*}}, [[SHD]]
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;EG-DAG: LSHL
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;EG-DAG: LSHL
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;EG-DAG: LSHL
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;EG-DAG: LSHL
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
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;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT {{.*}}, 0.0
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;EG-DAG: CNDE_INT
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;SI: {{^}}shl_v4i64:
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
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;VI: {{^}}shl_v4i64:
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
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define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
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%a = load <4 x i64>, <4 x i64> addrspace(1) * %in
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%b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
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%result = shl <4 x i64> %a, %b
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store <4 x i64> %result, <4 x i64> addrspace(1)* %out
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ret void
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}
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; Make sure load width gets reduced to i32 load.
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; GCN-LABEL: {{^}}s_shl_32_i64:
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; GCN-DAG: s_load_dword [[LO_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb{{$}}
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; GCN-DAG: s_mov_b32 s[[SLO:[0-9]+]], 0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]]
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; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[LO_A]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
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define void @s_shl_32_i64(i64 addrspace(1)* %out, i64 %a) {
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%result = shl i64 %a, 32
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store i64 %result, i64 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_shl_32_i64:
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; GCN-DAG: buffer_load_dword v[[LO_A:[0-9]+]],
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; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}}
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; GCN: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[LO_A]]{{\]}}
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define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
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%a = load i64, i64 addrspace(1)* %gep.in
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%result = shl i64 %a, 32
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store i64 %result, i64 addrspace(1)* %gep.out
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ret void
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}
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attributes #0 = { nounwind readnone }
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