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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
43 lines
1.0 KiB
YAML
43 lines
1.0 KiB
YAML
# RUN: llc -march=hexagon -run-pass if-converter %s -o - | FileCheck %s
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# Make sure that the necessary implicit uses are added to predicated
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# instructions.
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# CHECK-LABEL: name: foo
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--- |
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define void @foo() {
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ret void
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}
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...
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---
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name: foo
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $r0, $r2, $p1
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J2_jumpf $p1, %bb.1, implicit-def $pc
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J2_jump %bb.2, implicit-def $pc
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bb.1:
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successors: %bb.3
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liveins: $r2
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$r0 = A2_tfrsi 2
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J2_jump %bb.3, implicit-def $pc
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bb.2:
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successors: %bb.3
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liveins: $r0
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; Even though r2 was not live on entry to this block, it was live across
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; block bb.1 in the original diamond. After if-conversion, the diamond
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; became a single block, and so r2 is now live on entry to the instructions
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; originating from bb.2.
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; CHECK: $r2 = C2_cmoveit $p1, 1, implicit killed $r2
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$r2 = A2_tfrsi 1
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bb.3:
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liveins: $r0, $r2
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$r0 = A2_add $r0, $r2
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J2_jumpr $r31, implicit-def $pc
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...
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