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90db73a094
This patch assigns cost of the scaling used in addressing for Cortex-R52. On Cortex-R52 a negated register offset takes longer than a non-negated register offset, in a register-offset addressing mode. Differential Revision: http://reviews.llvm.org/D25670 Reviewer: jmolloy llvm-svn: 284460
29 lines
996 B
LLVM
29 lines
996 B
LLVM
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
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; Should use scaled addressing mode.
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
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; Should not generate negated register offset
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define void @sintzero(i32* %a) nounwind {
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entry:
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store i32 0, i32* %a
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br label %cond_next
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cond_next: ; preds = %cond_next, %entry
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%indvar = phi i32 [ 0, %entry ], [ %tmp25, %cond_next ] ; <i32> [#uses=1]
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%tmp25 = add i32 %indvar, 1 ; <i32> [#uses=3]
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%tmp36 = getelementptr i32, i32* %a, i32 %tmp25 ; <i32*> [#uses=1]
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store i32 0, i32* %tmp36
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icmp eq i32 %tmp25, -1 ; <i1>:0 [#uses=1]
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br i1 %0, label %return, label %cond_next
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return: ; preds = %cond_next
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ret void
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}
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; CHECK: lsl{{.*}}#2]
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; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
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