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168 lines
5.2 KiB
LLVM
168 lines
5.2 KiB
LLVM
; RUN: llc -O0 < %s | FileCheck %s
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;ModuleID = 'test.c'
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target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"
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target triple = "powerpc-unknown-freebsd9.0"
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%struct.__va_list_tag = type { i8, i8, i16, i8*, i8* }
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@var1 = common global i64 0, align 8
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@var2 = common global double 0.0, align 8
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@var3 = common global i32 0, align 4
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define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind {
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entry:
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%x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6
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; CHECK: lbz 4, 0(3)
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; CHECK-NEXT: lwz 5, 4(3)
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; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31
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; CHECK-NEXT: cmplwi 0, 6, 0
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; CHECK-NEXT: addi 6, 4, 1
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; CHECK-NEXT: stw 3, -4(1)
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; CHECK-NEXT: stw 6, -8(1)
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; CHECK-NEXT: stw 4, -12(1)
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; CHECK-NEXT: stw 5, -16(1)
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; CHECK-NEXT: bne 0, .LBB0_2
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; CHECK-NEXT: # BB#1: # %entry
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; CHECK-NEXT: lwz 3, -12(1)
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; CHECK-NEXT: stw 3, -8(1)
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; CHECK-NEXT: .LBB0_2: # %entry
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; CHECK-NEXT: lwz 3, -8(1)
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; CHECK-NEXT: lwz 4, -4(1)
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; CHECK-NEXT: lwz 5, 8(4)
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; CHECK-NEXT: slwi 6, 3, 2
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; CHECK-NEXT: addi 7, 3, 2
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: lwz 3, -16(1)
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; CHECK-NEXT: addi 8, 3, 4
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; CHECK-NEXT: add 5, 5, 6
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -20(1)
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; CHECK-NEXT: stw 5, -24(1)
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; CHECK-NEXT: stw 3, -28(1)
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; CHECK-NEXT: stw 7, -32(1)
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; CHECK-NEXT: stw 8, -36(1)
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; CHECK-NEXT: blt 0, .LBB0_4
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; CHECK-NEXT: # BB#3: # %entry
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; CHECK-NEXT: lwz 3, -36(1)
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; CHECK-NEXT: stw 3, -28(1)
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; CHECK-NEXT: .LBB0_4: # %entry
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; CHECK-NEXT: lwz 3, -28(1)
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; CHECK-NEXT: lwz 4, -32(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 0(5)
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; CHECK-NEXT: lwz 4, -24(1)
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; CHECK-NEXT: lwz 0, -20(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 3, -40(1)
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; CHECK-NEXT: stw 4, -44(1)
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; CHECK-NEXT: blt 0, .LBB0_6
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; CHECK-NEXT: # BB#5: # %entry
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; CHECK-NEXT: lwz 3, -16(1)
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; CHECK-NEXT: stw 3, -44(1)
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; CHECK-NEXT: .LBB0_6: # %entry
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; CHECK-NEXT: lwz 3, -44(1)
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; CHECK-NEXT: lwz 4, -40(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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store i64 %x, i64* @var1, align 8
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; CHECK-NEXT: lis 4, var1@ha
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; CHECK-NEXT: lwz 6, 4(3)
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; CHECK-NEXT: lwz 3, 0(3)
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; CHECK-NEXT: la 7, var1@l(4)
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; CHECK-NEXT: stw 3, var1@l(4)
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; CHECK-NEXT: stw 6, 4(7)
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%y = va_arg %struct.__va_list_tag* %ap, double; From f1
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; CHECK-NEXT: lbz 3, 1(5)
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; CHECK-NEXT: lwz 4, 4(5)
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; CHECK-NEXT: lwz 6, 8(5)
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; CHECK-NEXT: slwi 7, 3, 3
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; CHECK-NEXT: add 6, 6, 7
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; CHECK-NEXT: addi 7, 3, 1
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 3, 4, 8
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; CHECK-NEXT: addi 6, 6, 32
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; CHECK-NEXT: mr 8, 4
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -48(1)
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; CHECK-NEXT: stw 4, -52(1)
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; CHECK-NEXT: stw 6, -56(1)
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; CHECK-NEXT: stw 7, -60(1)
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; CHECK-NEXT: stw 3, -64(1)
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; CHECK-NEXT: stw 8, -68(1)
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; CHECK-NEXT: blt 0, .LBB0_8
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; CHECK-NEXT: # BB#7: # %entry
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; CHECK-NEXT: lwz 3, -64(1)
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; CHECK-NEXT: stw 3, -68(1)
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; CHECK-NEXT: .LBB0_8: # %entry
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; CHECK-NEXT: lwz 3, -68(1)
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; CHECK-NEXT: lwz 4, -60(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 1(5)
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; CHECK-NEXT: lwz 4, -56(1)
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; CHECK-NEXT: lwz 0, -48(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -72(1)
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; CHECK-NEXT: stw 3, -76(1)
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; CHECK-NEXT: blt 0, .LBB0_10
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; CHECK-NEXT: # BB#9: # %entry
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; CHECK-NEXT: lwz 3, -52(1)
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; CHECK-NEXT: stw 3, -72(1)
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; CHECK-NEXT: .LBB0_10: # %entry
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; CHECK-NEXT: lwz 3, -72(1)
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; CHECK-NEXT: lwz 4, -76(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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; CHECK-NEXT: lfd 0, 0(3)
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store double %y, double* @var2, align 8
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; CHECK-NEXT: lis 3, var2@ha
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; CHECK-NEXT: stfd 0, var2@l(3)
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%z = va_arg %struct.__va_list_tag* %ap, i32; From r7
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; CHECK-NEXT: lbz 3, 0(5)
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; CHECK-NEXT: lwz 4, 4(5)
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; CHECK-NEXT: lwz 6, 8(5)
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; CHECK-NEXT: slwi 7, 3, 2
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; CHECK-NEXT: addi 8, 3, 1
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; CHECK-NEXT: cmpwi 0, 3, 8
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; CHECK-NEXT: addi 3, 4, 4
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; CHECK-NEXT: add 6, 6, 7
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; CHECK-NEXT: mr 7, 4
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; CHECK-NEXT: stw 6, -80(1)
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; CHECK-NEXT: stw 8, -84(1)
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; CHECK-NEXT: stw 3, -88(1)
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; CHECK-NEXT: stw 4, -92(1)
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; CHECK-NEXT: stw 7, -96(1)
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; CHECK-NEXT: mfcr 0 # cr0
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; CHECK-NEXT: stw 0, -100(1)
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; CHECK-NEXT: blt 0, .LBB0_12
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; CHECK-NEXT: # BB#11: # %entry
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; CHECK-NEXT: lwz 3, -88(1)
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; CHECK-NEXT: stw 3, -96(1)
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; CHECK-NEXT: .LBB0_12: # %entry
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; CHECK-NEXT: lwz 3, -96(1)
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; CHECK-NEXT: lwz 4, -84(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stb 4, 0(5)
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; CHECK-NEXT: lwz 4, -80(1)
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; CHECK-NEXT: lwz 0, -100(1)
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; CHECK-NEXT: mtcrf 128, 0
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; CHECK-NEXT: stw 4, -104(1)
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; CHECK-NEXT: stw 3, -108(1)
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; CHECK-NEXT: blt 0, .LBB0_14
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; CHECK-NEXT: # BB#13: # %entry
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; CHECK-NEXT: lwz 3, -92(1)
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; CHECK-NEXT: stw 3, -104(1)
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; CHECK-NEXT: .LBB0_14: # %entry
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; CHECK-NEXT: lwz 3, -104(1)
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; CHECK-NEXT: lwz 4, -108(1)
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; CHECK-NEXT: lwz 5, -4(1)
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; CHECK-NEXT: stw 4, 4(5)
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; CHECK-NEXT: lwz 3, 0(3)
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store i32 %z, i32* @var3, align 4
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; CHECK-NEXT: lis 4, var3@ha
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; CHECK-NEXT: stw 3, var3@l(4)
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ret void
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; CHECK-NEXT: stw 5, -112(1)
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; CHECK-NEXT: blr
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}
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