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https://reviews.llvm.org/D70210 Previously: Due to sensitivity of the algorithm with gaps, and extra instructions, when diffing, often we see naming being off by a few. Makes the diff unreadable even for tests with 7 and 8 instructions respectively. Naming can change depending on candidates (and order of picking candidates). Suddenly if there's one extra instruction somewhere, the entire subtree would be named completely differently. No consistent naming of similar instructions which occur in different functions. If we try to do something like count the frequency distribution of various differences across suite, then the above sensitivity issues are going to result in poor results. Instead: Name instruction based on semantics of the instruction (hash of the opcode and operands). Essentially for a given instruction that occurs in any module/function it'll be named similarly (ie semantic). This has some nice properties Can easily look at many instructions and just check the hash and if they're named similarly, then it's the same instruction. Makes it very easy to spot the same instruction both multiple times, as well as across many functions (useful for frequency distribution). Independent of traversal/candidates/depth of graph. No need to keep track of last index/gaps/skip count etc. No off by few issues with diffs. I've tried the old vs new implementation in files ranging from 30 to 700 instructions. In both cases with the old algorithm, diffs are a sea of red, where as for the semantic version, in both cases, the diffs line up beautifully. Simplified implementation of the main loop (simple iteration) , no keep track of what's visited and not. Handle collision just by incrementing a counter. Roughly bb[N]_hash_[CollisionCount]. Additionally with the new implementation, we can probably avoid doing the hoisting of instructions to various places, as they'll likely be named the same resulting in differences only based on collision (ie regardless of whether the instruction is hoisted or not/close to use or not, it'll be named the same hash which should result in use of the instruction be identical with the only change being the collision count) which is very easy to spot visually.
79 lines
2.1 KiB
C++
79 lines
2.1 KiB
C++
//===----------------------- MIRNamer.cpp - MIR Namer ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The purpose of this pass is to rename virtual register operands with the goal
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// of making it easier to author easier to read tests for MIR. This pass reuses
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// the vreg renamer used by MIRCanonicalizerPass.
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//
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// Basic Usage:
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//
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// llc -o - -run-pass mir-namer example.mir
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//
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//===----------------------------------------------------------------------===//
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#include "MIRVRegNamerUtils.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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namespace llvm {
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extern char &MIRNamerID;
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} // namespace llvm
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#define DEBUG_TYPE "mir-namer"
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namespace {
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class MIRNamer : public MachineFunctionPass {
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public:
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static char ID;
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MIRNamer() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "Rename virtual register operands";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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bool Changed = false;
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if (MF.empty())
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return Changed;
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VRegRenamer Renamer(MF.getRegInfo());
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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for (auto &MBB : RPOT)
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Changed |= Renamer.renameVRegs(MBB);
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return Changed;
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}
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};
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} // end anonymous namespace
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char MIRNamer::ID;
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char &llvm::MIRNamerID = MIRNamer::ID;
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INITIALIZE_PASS_BEGIN(MIRNamer, "mir-namer", "Rename Register Operands", false,
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false)
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INITIALIZE_PASS_END(MIRNamer, "mir-namer", "Rename Register Operands", false,
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false)
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