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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
llvm-mirror/lib/Target/Alpha
2011-10-13 23:13:35 +00:00
..
MCTargetDesc Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
TargetInfo Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
Alpha.h Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
Alpha.td Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00
AlphaAsmPrinter.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaFrameLowering.cpp Teach frame lowering to ignore debug values after the terminators. 2011-01-13 21:28:52 +00:00
AlphaFrameLowering.h Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
AlphaInstrFormats.td
AlphaInstrInfo.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaInstrInfo.h Hide the call to InitMCInstrInfo into tblgen generated ctor. 2011-07-01 17:57:27 +00:00
AlphaInstrInfo.td Code generation for 'fence' instruction. 2011-07-27 22:21:52 +00:00
AlphaISelDAGToDAG.cpp Fix undefined shifts and abs in Alpha backend. Based on patch by Ahmed Charles. 2011-10-13 23:13:35 +00:00
AlphaISelLowering.cpp Add codegen support for vector select (in the IR this means a select 2011-09-06 19:07:46 +00:00
AlphaISelLowering.h Add codegen support for vector select (in the IR this means a select 2011-09-06 19:07:46 +00:00
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaRegisterInfo.cpp Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 2011-07-18 22:29:13 +00:00
AlphaRegisterInfo.h Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 2011-07-18 20:57:22 +00:00
AlphaRegisterInfo.td Use set operations instead of plain lists to enumerate register classes. 2011-06-15 23:28:14 +00:00
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaSubtarget.h Compute feature bits at time of MCSubtargetInfo initialization. 2011-07-07 07:07:08 +00:00
AlphaTargetMachine.cpp Move TargetRegistry and TargetSelect from Target to Support where they belong. 2011-08-24 18:08:43 +00:00
AlphaTargetMachine.h - Move CodeModel from a TargetMachine global option to MCCodeGenInfo. 2011-07-20 07:51:56 +00:00
CMakeLists.txt Build system infrastructure for multiple tblgens. 2011-10-06 01:51:51 +00:00
Makefile Next round of MC refactoring. This patch factor MC table instantiations, MC 2011-07-14 20:59:42 +00:00
README.txt Fix a ton of comment typos found by codespell. Patch by 2011-04-15 05:18:47 +00:00

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum across bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extensions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html