mirror of
https://github.com/RPCS3/llvm-mirror.git
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261 lines
8.8 KiB
YAML
261 lines
8.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: urem_s32_var_const0
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: urem_s32_var_const0
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; GCN: liveins: $vgpr0
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: %const:_(s32) = G_CONSTANT i32 0
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; GCN: %rem:_(s32) = G_UREM %var, %const
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; GCN: $vgpr0 = COPY %rem(s32)
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%var:_(s32) = COPY $vgpr0
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%const:_(s32) = G_CONSTANT i32 0
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%rem:_(s32) = G_UREM %var, %const
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$vgpr0 = COPY %rem
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...
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---
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name: urem_s32_var_const1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: urem_s32_var_const1
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; GCN: liveins: $vgpr0
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GCN: $vgpr0 = COPY [[C]](s32)
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%var:_(s32) = COPY $vgpr0
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%const:_(s32) = G_CONSTANT i32 1
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%rem:_(s32) = G_UREM %var, %const
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$vgpr0 = COPY %rem
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...
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---
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name: urem_s32_var_const2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: urem_s32_var_const2
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; GCN: liveins: $vgpr0
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; GCN: %rem:_(s32) = G_AND %var, [[C]]
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; GCN: $vgpr0 = COPY %rem(s32)
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%var:_(s32) = COPY $vgpr0
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%const:_(s32) = G_CONSTANT i32 2
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%rem:_(s32) = G_UREM %var, %const
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$vgpr0 = COPY %rem
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...
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---
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name: urem_s32_var_shl1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: urem_s32_var_shl1
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: %var:_(s32) = COPY $vgpr0
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; GCN: %shift_amt:_(s32) = COPY $vgpr1
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; GCN: %one:_(s32) = G_CONSTANT i32 1
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; GCN: %one_bit:_(s32) = G_SHL %one, %shift_amt(s32)
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; GCN: [[ADD:%[0-9]+]]:_(s32) = G_ADD %one_bit, [[C]]
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; GCN: %rem:_(s32) = G_AND %var, [[ADD]]
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; GCN: $vgpr0 = COPY %rem(s32)
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%var:_(s32) = COPY $vgpr0
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%shift_amt:_(s32) = COPY $vgpr1
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%one:_(s32) = G_CONSTANT i32 1
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%one_bit:_(s32) = G_SHL %one, %shift_amt
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%rem:_(s32) = G_UREM %var, %one_bit
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$vgpr0 = COPY %rem
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...
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---
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name: urem_s64_var_shl1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2
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; GCN-LABEL: name: urem_s64_var_shl1
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2
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; GCN: %var:_(s64) = COPY $vgpr0_vgpr1
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; GCN: %shiftamt:_(s32) = COPY $vgpr2
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; GCN: %one:_(s64) = G_CONSTANT i64 1
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; GCN: %one_bit:_(s64) = G_SHL %one, %shiftamt(s32)
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; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
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; GCN: [[ADD:%[0-9]+]]:_(s64) = G_ADD %one_bit, [[C]]
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; GCN: %rem:_(s64) = G_AND %var, [[ADD]]
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; GCN: $vgpr0_vgpr1 = COPY %rem(s64)
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%var:_(s64) = COPY $vgpr0_vgpr1
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%shiftamt:_(s32) = COPY $vgpr2
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%one:_(s64) = G_CONSTANT i64 1
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%one_bit:_(s64) = G_SHL %one, %shiftamt
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%rem:_(s64) = G_UREM %var, %one_bit
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$vgpr0_vgpr1 = COPY %rem
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...
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---
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name: urem_v2s32_var_shl1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN-LABEL: name: urem_v2s32_var_shl1
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; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
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; GCN: %one:_(s32) = G_CONSTANT i32 1
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; GCN: %one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one(s32), %one(s32)
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; GCN: %one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt(<2 x s32>)
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; GCN: %rem:_(<2 x s32>) = G_UREM %var, %one_bit
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; GCN: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%shift_amt:_(<2 x s32>) = COPY $vgpr2_vgpr3
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%one:_(s32) = G_CONSTANT i32 1
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%one_vec:_(<2 x s32>) = G_BUILD_VECTOR %one, %one
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%one_bit:_(<2 x s32>) = G_SHL %one_vec, %shift_amt
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%rem:_(<2 x s32>) = G_UREM %var, %one_bit
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$vgpr0_vgpr1 = COPY %rem
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...
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---
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name: urem_v2s16_var_const4_build_vector_trunc
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: urem_v2s16_var_const4_build_vector_trunc
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: %var:_(<2 x s16>) = COPY $vgpr0
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; GCN: %four:_(s32) = G_CONSTANT i32 4
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; GCN: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %four(s32)
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; GCN: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 -1
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; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
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; GCN: [[ADD:%[0-9]+]]:_(<2 x s16>) = G_ADD %four_vec, [[BUILD_VECTOR]]
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; GCN: %rem:_(<2 x s16>) = G_AND %var, [[ADD]]
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; GCN: $vgpr0 = COPY %rem(<2 x s16>)
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%var:_(<2 x s16>) = COPY $vgpr0
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%shift_amt:_(s32) = COPY $vgpr1
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%four:_(s32) = G_CONSTANT i32 4
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%four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %four
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%rem:_(<2 x s16>) = G_UREM %var, %four_vec
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$vgpr0 = COPY %rem
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...
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# The shl is a known power of two, but we do not know if the final
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# value is a power of 2 due to the truncation.
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---
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name: urem_v2s16_var_nonconst_build_vector_trunc
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: urem_v2s16_var_nonconst_build_vector_trunc
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN: %var:_(<2 x s16>) = COPY $vgpr0
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; GCN: %shift_amt:_(<2 x s16>) = COPY $vgpr1
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; GCN: %two:_(s32) = G_CONSTANT i32 2
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; GCN: %four:_(s32) = G_CONSTANT i32 4
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; GCN: %shift:_(s32) = G_SHL %two, %shift_amt(<2 x s16>)
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; GCN: %four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four(s32), %shift(s32)
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; GCN: %rem:_(<2 x s16>) = G_UREM %var, %four_vec
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; GCN: $vgpr0 = COPY %rem(<2 x s16>)
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%var:_(<2 x s16>) = COPY $vgpr0
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%shift_amt:_(<2 x s16>) = COPY $vgpr1
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%two:_(s32) = G_CONSTANT i32 2
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%four:_(s32) = G_CONSTANT i32 4
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%shift:_(s32) = G_SHL %two, %shift_amt
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%four_vec:_(<2 x s16>) = G_BUILD_VECTOR_TRUNC %four, %shift
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%rem:_(<2 x s16>) = G_UREM %var, %four_vec
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$vgpr0 = COPY %rem
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...
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---
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name: v_urem_v2i32_pow2k_denom
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: v_urem_v2i32_pow2k_denom
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %pow2:_(s32) = G_CONSTANT i32 4096
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; GCN: %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2(s32), %pow2(s32)
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; GCN: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD %pow2_vec, [[BUILD_VECTOR]]
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; GCN: %rem:_(<2 x s32>) = G_AND %var, [[ADD]]
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; GCN: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%pow2:_(s32) = G_CONSTANT i32 4096
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%pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2(s32), %pow2(s32)
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%rem:_(<2 x s32>) = G_UREM %var, %pow2_vec
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$vgpr0_vgpr1 = COPY %rem
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...
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---
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name: v_urem_v2i32_pow2k_not_splat_denom
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; GCN-LABEL: name: v_urem_v2i32_pow2k_not_splat_denom
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: %var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; GCN: %pow2_1:_(s32) = G_CONSTANT i32 4096
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; GCN: %pow2_2:_(s32) = G_CONSTANT i32 2048
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; GCN: %pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2_1(s32), %pow2_2(s32)
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; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; GCN: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD %pow2_vec, [[BUILD_VECTOR]]
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; GCN: %rem:_(<2 x s32>) = G_AND %var, [[ADD]]
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; GCN: $vgpr0_vgpr1 = COPY %rem(<2 x s32>)
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%var:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%pow2_1:_(s32) = G_CONSTANT i32 4096
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%pow2_2:_(s32) = G_CONSTANT i32 2048
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%pow2_vec:_(<2 x s32>) = G_BUILD_VECTOR %pow2_1(s32), %pow2_2(s32)
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%rem:_(<2 x s32>) = G_UREM %var, %pow2_vec
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$vgpr0_vgpr1 = COPY %rem
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...
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---
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name: v_urem_v2i64_pow2k_denom
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN-LABEL: name: v_urem_v2i64_pow2k_denom
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; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN: %var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; GCN: %pow2:_(s64) = G_CONSTANT i64 4096
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; GCN: %pow2_vec:_(<2 x s64>) = G_BUILD_VECTOR %pow2(s64), %pow2(s64)
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; GCN: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
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; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
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; GCN: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD %pow2_vec, [[BUILD_VECTOR]]
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; GCN: %rem:_(<2 x s64>) = G_AND %var, [[ADD]]
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; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem(<2 x s64>)
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%var:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%pow2:_(s64) = G_CONSTANT i64 4096
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%pow2_vec:_(<2 x s64>) = G_BUILD_VECTOR %pow2(s64), %pow2(s64)
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%rem:_(<2 x s64>) = G_UREM %var, %pow2_vec
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %rem
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...
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