| .. |
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add_shl.ll
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[AMDGPU] Make some VOP3 insts commutable
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2021-04-28 13:59:08 -04:00 |
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add.v2i16.ll
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[AMDGPU] Extend gfx10 test coverage. NFC.
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2021-03-29 11:13:55 +02:00 |
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amdgpu-irtranslator.ll
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andn2.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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artifact-combiner-anyext.mir
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artifact-combiner-build-vector.mir
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GlobalISel: Revisit users of other merge opcodes in artifact combiner
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2020-08-17 13:56:53 -04:00 |
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artifact-combiner-concat-vectors.mir
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GlobalISel: Revisit users of other merge opcodes in artifact combiner
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2020-08-17 13:56:53 -04:00 |
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artifact-combiner-extract.mir
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artifact-combiner-sext.mir
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artifact-combiner-trunc.mir
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artifact-combiner-unmerge-values.mir
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GlobalISel: Artifact combine unmerge of unmerge
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2020-09-01 11:01:33 -04:00 |
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artifact-combiner-zext.mir
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GlobalISel: Preserve LLT when bitcasting loads and stores
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2021-07-19 11:30:14 -04:00 |
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ashr.ll
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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atomic_optimizations_mul_one.ll
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[AMDGPU] Do not generate mul with 1 in AMDGPU Atomic Optimizer
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2020-09-30 11:09:18 +02:00 |
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bool-legalization.ll
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[AMDGPU] Add volatile support to SIMemoryLegalizer
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2021-01-09 00:52:33 +00:00 |
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bswap.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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buffer-schedule.ll
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[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
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2021-07-26 14:27:30 +01:00 |
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combine-add-nullptr.mir
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[GlobalISel] Avoid making G_PTR_ADD with nullptr
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2020-10-13 13:02:55 +02:00 |
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combine-add-to-ptradd.mir
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GlobalISel: Combine G_ADD of G_PTRTOINT to G_PTR_ADD
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2020-08-26 08:57:15 -04:00 |
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combine-amdgpu-cvt-f32-ubyte.mir
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GlobalISel: Add combines for extend operations
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2020-09-01 08:50:06 -07:00 |
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combine-ashr-narrow.mir
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combine-ext-legalizer.mir
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combine-fcanonicalize.mir
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AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
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2021-04-27 12:26:37 +02:00 |
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combine-itofp.mir
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combine-lshr-narrow.mir
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combine-or-redundant.mir
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[GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x
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2020-11-10 11:32:13 +01:00 |
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combine-redundant-and.mir
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[GlobalISel] Implement computeKnownBits for G_SEXT_INREG
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2021-01-26 15:01:38 -08:00 |
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combine-sext-inreg.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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combine-shift-imm-chain-illegal-types.mir
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[AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands
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2020-11-10 11:32:12 +01:00 |
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combine-shift-imm-chain-shlsat.mir
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[AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands
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2020-11-10 11:32:12 +01:00 |
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combine-shift-imm-chain.ll
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[AMDGPU][GlobalISel] Fold a chain of two shift instructions with constant operands
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2020-11-10 11:32:12 +01:00 |
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combine-shift-of-shifted-logic-shlsat.mir
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[AMDGPU][GlobalISel] Combine shift + logic + shift with constant operands
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2020-11-10 11:32:13 +01:00 |
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combine-shift-of-shifted-logic.ll
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[GlobalISel] Add combine for (x | mask) -> x when (x | mask) == x
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2020-11-10 11:32:13 +01:00 |
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combine-shl-from-extend-narrow.postlegal.mir
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GlobalISel: Reduce G_SHL width if source is extension
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2020-08-24 09:42:40 -04:00 |
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combine-shl-from-extend-narrow.prelegal.mir
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GlobalISel: Add combines for extend operations
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2020-09-01 08:50:06 -07:00 |
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combine-shl-narrow.mir
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[GlobalISel] Add X,Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z
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2020-09-14 17:27:23 -07:00 |
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combine-short-clamp.ll
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[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
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2021-04-01 14:21:00 +03:00 |
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combine-trunc-shl.mir
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GlobalISel: Fix truncating shift amount in trunc (shl) combine
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2020-09-23 09:07:50 -04:00 |
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combine-urem-pow-2.mir
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GlobalISel: Handle G_BUILD_VECTOR in isKnownToBeAPowerOfTwo
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2021-03-22 14:20:35 -04:00 |
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combine-zext-trunc.mir
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Reland [GlobalISel] Combine zext(trunc x) to x
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2021-03-05 11:05:37 +01:00 |
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constant-bus-restriction.ll
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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cvt_f32_ubyte.ll
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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divergent-control-flow.ll
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Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
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2021-03-05 11:05:37 +01:00 |
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dummy-target.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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dynamic-alloca-divergent.ll
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dynamic-alloca-uniform.ll
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[AMDGPU] Init scratch only if necessary
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2021-07-14 10:45:22 +02:00 |
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extractelement-stack-lower.ll
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RegAlloc: Allow targets to split register allocation
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2021-07-13 18:49:29 -04:00 |
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extractelement.i8.ll
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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extractelement.i16.ll
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[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
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2021-04-26 17:21:49 -04:00 |
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extractelement.i128.ll
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[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
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2021-04-26 17:21:49 -04:00 |
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extractelement.ll
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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fdiv.f16.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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fdiv.f32.ll
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[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
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2021-04-26 17:21:49 -04:00 |
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fdiv.f64.ll
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[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
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2021-04-26 17:21:49 -04:00 |
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flat-scratch-init.ll
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[AMDGPU] Init scratch only if necessary
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2021-07-14 10:45:22 +02:00 |
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flat-scratch.ll
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[AMDGPU] Use s_add_i32 for address additions
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2021-06-07 16:09:48 +02:00 |
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floor.f64.ll
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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fma.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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fmax_legacy.ll
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Revert "[AMDGPU] Insert waitcnt after returning from call"
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2020-09-23 17:16:39 +02:00 |
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fmed3.ll
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AMDGPU/GlobalISel: Remove redundant G_FCANONICALIZE
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2021-04-27 12:26:37 +02:00 |
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fmin_legacy.ll
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Revert "[AMDGPU] Insert waitcnt after returning from call"
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2020-09-23 17:16:39 +02:00 |
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fmul.v2f16.ll
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[AMDGPU] Extend gfx10 test coverage. NFC.
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2021-03-29 11:13:55 +02:00 |
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fp64-atomics-gfx90a.ll
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[AMDGPU] gfx90a support
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2021-02-17 16:01:32 -08:00 |
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fpow.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
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2021-05-05 17:35:02 -04:00 |
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frem.ll
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GlobalISel: Avoid use of G_INSERT in insertParts
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2021-06-08 14:44:24 -04:00 |
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fshl.ll
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[GlobalISel] Add a constant folding combine.
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2021-07-26 14:53:33 -07:00 |
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fshr.ll
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[GlobalISel] Add a constant folding combine.
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2021-07-26 14:53:33 -07:00 |
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function-returns.ll
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GlobalISel: Preserve memory types for implicit sret load/stores
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2021-07-19 11:52:42 -04:00 |
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global-value.illegal.ll
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global-value.ll
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AMDGPU/GlobalISel: Preserve more memory types
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2021-07-16 08:57:26 -04:00 |
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hip.extern.shared.array.ll
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[amdgpu] Add codegen support for HIP dynamic shared memory.
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2020-08-20 21:29:18 -04:00 |
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image_ls_mipmap_zero.a16.ll
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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image_ls_mipmap_zero.ll
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inline-asm.ll
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Reapply "RegAllocFast: Rewrite and improve"
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2020-09-30 10:35:25 -04:00 |
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insertelement-stack-lower.ll
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AMDGPU/GlobalISel: Improve private addressing mode matching
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2021-03-11 10:23:35 -05:00 |
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insertelement.i8.ll
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[AMDGPU] Fix flags of V_MOV_B64_PSEUDO
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2021-07-09 12:49:28 -07:00 |
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insertelement.i16.ll
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[AMDGPU] Fix flags of V_MOV_B64_PSEUDO
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2021-07-09 12:49:28 -07:00 |
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insertelement.large.ll
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[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices
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2021-04-01 14:21:00 +03:00 |
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insertelement.ll
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[AMDGPU] Add 224-bit vector types and link 192-bit types to MVTs
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2021-06-24 12:41:22 +09:00 |
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inst-select-abs.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
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2021-03-29 11:13:55 +02:00 |
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inst-select-add.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
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2021-03-29 11:13:55 +02:00 |
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inst-select-add.s16.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.class.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-amdgcn.class.s16.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-amdgcn.cos.mir
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inst-select-amdgcn.cos.s16.mir
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inst-select-amdgcn.cvt.pk.i16.mir
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inst-select-amdgcn.cvt.pk.u16.mir
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inst-select-amdgcn.cvt.pknorm.i16.mir
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inst-select-amdgcn.cvt.pknorm.u16.mir
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inst-select-amdgcn.cvt.pkrtz.mir
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inst-select-amdgcn.ds.swizzle.mir
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inst-select-amdgcn.exp.mir
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inst-select-amdgcn.fmad.ftz.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fmed3.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fmed3.s16.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.fract.mir
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inst-select-amdgcn.fract.s16.mir
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inst-select-amdgcn.groupstaticsize.mir
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AMDGPU/GlobalISel: Select llvm.amdgcn.groupstaticsize
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2020-08-18 09:28:01 -04:00 |
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inst-select-amdgcn.ldexp.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-amdgcn.ldexp.s16.mir
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inst-select-amdgcn.mbcnt.lo.mir
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inst-select-amdgcn.mul.u24.mir
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inst-select-amdgcn.rcp.legacy.mir
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inst-select-amdgcn.rcp.mir
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inst-select-amdgcn.rcp.s16.mir
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inst-select-amdgcn.readfirstlane.mir
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inst-select-amdgcn.reloc.constant.mir
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inst-select-amdgcn.rsq.clamp.mir
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inst-select-amdgcn.rsq.legacy.mir
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inst-select-amdgcn.rsq.mir
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inst-select-amdgcn.rsq.s16.mir
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inst-select-amdgcn.s.barrier.mir
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inst-select-amdgcn.s.sendmsg.mir
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inst-select-amdgcn.sffbh.mir
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inst-select-amdgcn.sin.mir
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inst-select-amdgcn.sin.s16.mir
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inst-select-amdgpu-atomic-cmpxchg-flat.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-amdgpu-atomic-cmpxchg-global.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-amdgpu-ffbh-u32.mir
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inst-select-and.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-anyext.mir
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inst-select-ashr.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-ashr.s16.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-ashr.v2s16.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-atomic-cmpxchg-local.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomic-cmpxchg-region.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-add-flat.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-add-global.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-fadd-local.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-fadd-region.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-xchg-local.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-atomicrmw-xchg-region.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-bitcast.mir
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inst-select-bitreverse.mir
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[AMDGPU] Better codegen for i64 bitreverse
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2021-02-26 15:51:36 +00:00 |
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inst-select-br.mir
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inst-select-brcond.mir
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inst-select-bswap.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
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2021-01-12 18:33:18 -05:00 |
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inst-select-build-vector-trunc.v2s16.mir
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[AMDGPU][GlobalISel] Avoid selecting S_PACK with constants
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2021-01-20 11:54:53 +01:00 |
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inst-select-build-vector.mir
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inst-select-concat-vectors.mir
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inst-select-constant.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-copy.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-ctlz-zero-undef.mir
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inst-select-ctpop.mir
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inst-select-cttz-zero-undef.mir
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inst-select-extract-vector-elt.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-extract.mir
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inst-select-fabs.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fadd.s16.mir
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inst-select-fadd.s32.mir
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inst-select-fadd.s64.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-fcanonicalize.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fceil.mir
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inst-select-fceil.s16.mir
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inst-select-fcmp.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
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2020-12-02 10:11:42 +00:00 |
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inst-select-fcmp.s16.mir
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[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
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inst-select-fconstant.mir
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AMDGPU/GlobalISel: Fix selection of s1/s16 G_[F]CONSTANT
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2020-08-18 09:28:01 -04:00 |
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inst-select-fexp2.mir
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inst-select-ffloor.s16.mir
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inst-select-ffloor.s32.mir
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inst-select-ffloor.s64.mir
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inst-select-fma.s32.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-fmad.s32.mir
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[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
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inst-select-fmaxnum-ieee.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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inst-select-fmaxnum-ieee.s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fmaxnum-ieee.v2s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fmaxnum.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-fmaxnum.s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fmaxnum.v2s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fminnum-ieee.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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inst-select-fminnum-ieee.s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fminnum-ieee.v2s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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inst-select-fminnum.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
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inst-select-fminnum.s16.mir
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[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fminnum.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fmul.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fmul.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fneg.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-fptosi.mir
|
[AMDGPU] Add Fiji target in fptosi/fptoui instruction-select MIR tests.
|
2021-02-05 11:33:54 -06:00 |
|
inst-select-fptoui.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-fract.f64.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-frame-index.mir
|
|
|
|
inst-select-freeze.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-frint.mir
|
|
|
|
inst-select-frint.s16.mir
|
|
|
|
inst-select-fshr.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-icmp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-icmp.s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-icmp.s64.mir
|
|
|
|
inst-select-implicit-def.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-insert-vector-elt.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-insert.mir
|
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
|
2021-04-30 14:10:50 +01:00 |
|
inst-select-insert.xfail.mir
|
|
|
|
inst-select-intrinsic-trunc.mir
|
|
|
|
inst-select-intrinsic-trunc.s16.mir
|
|
|
|
inst-select-inttoptr.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-atomic-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-atomic-global.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-atomic-local.mir
|
AMDGPU/GlobalISel: Fix some incorrect memory types in tests
|
2021-07-16 20:20:55 -04:00 |
|
inst-select-load-constant.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-global-saddr.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-global.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-global.s96.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-local-128.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-private.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-load-smrd.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-lshr.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-lshr.s16.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-lshr.v2s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-merge-values.mir
|
|
|
|
inst-select-mul.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-or.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-pattern-add3.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-and-or.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-or3.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-smed3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-pattern-smed3.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-umed3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-pattern-umed3.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-pattern-xor3.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-phi.mir
|
|
|
|
inst-select-ptr-add.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-ptrmask.mir
|
|
|
|
inst-select-ptrtoint.mir
|
|
|
|
inst-select-returnaddress.mir
|
|
|
|
inst-select-sbfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
inst-select-scalar-packed.xfail.mir
|
|
|
|
inst-select-select.mir
|
|
|
|
inst-select-sext-inreg.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-sext.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-sextload-local.mir
|
AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9
|
2021-07-27 15:56:42 -04:00 |
|
inst-select-shl.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-shl.s16.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-shl.v2s16.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-shuffle-vector.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-sitofp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-smax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-smin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-smulh.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-store-atomic-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-atomic-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-global.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-global.s96.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
inst-select-store-private.mir
|
AMDGPU/GlobalISel: Fix some incorrect memory types in tests
|
2021-07-16 20:20:55 -04:00 |
|
inst-select-sub.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-trunc.mir
|
AMDGPU/GlobalISel: re-auto-generate some test checks
|
2020-08-25 15:54:22 +01:00 |
|
inst-select-trunc.v2s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-uadde.gfx10.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-uadde.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-uaddo.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-ubfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
inst-select-uitofp.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-umax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-umin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-umulh.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
inst-select-unmerge-values.mir
|
|
|
|
inst-select-usube.gfx10.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-usube.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-usubo.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-xor.mir
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
inst-select-zext.mir
|
[AMDGPU] Add _e64 suffix to VOP3 Insts
|
2021-01-12 18:33:18 -05:00 |
|
inst-select-zextload-local.mir
|
AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9
|
2021-07-27 15:56:42 -04:00 |
|
irtranslator-amdgcn-sendmsg.ll
|
AMDGPU/GlobalISel: re-auto-generate some test checks
|
2020-08-25 15:54:22 +01:00 |
|
irtranslator-amdgpu_kernel-system-sgprs.ll
|
|
|
|
irtranslator-amdgpu_kernel.ll
|
AMDGPU/GlobalISel: Preserve more memory types
|
2021-07-16 08:57:26 -04:00 |
|
irtranslator-amdgpu_ps.ll
|
|
|
|
irtranslator-amdgpu_vs.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-atomicrmw.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-call-implicit-args.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-call-non-fixed.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-call-return-values.ll
|
GlobalISel: Preserve memory types for implicit sret load/stores
|
2021-07-19 11:52:42 -04:00 |
|
irtranslator-call-sret.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-call.ll
|
GlobalISel: Track argument pointeriness with arg flags
|
2021-07-15 19:11:40 -04:00 |
|
irtranslator-constantexpr.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-constrained-fp.ll
|
GlobalISel: Merge some AMDGPU ABI lowering code to generic code
|
2021-02-18 17:26:55 -05:00 |
|
irtranslator-fast-math-flags.ll
|
|
|
|
irtranslator-fence.ll
|
|
|
|
irtranslator-fixed-function-abi-vgpr-args.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-function-args.ll
|
AMDGPU/GlobalISel: Add a few tests for struct arguments
|
2021-07-16 20:20:55 -04:00 |
|
irtranslator-getelementptr.ll
|
GlobalISel: Merge some AMDGPU ABI lowering code to generic code
|
2021-02-18 17:26:55 -05:00 |
|
irtranslator-indirect-call.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-inline-asm.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-memory-intrinsics.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-metadata.ll
|
|
|
|
irtranslator-ptrmask.ll
|
GlobalISel: Merge some AMDGPU ABI lowering code to generic code
|
2021-02-18 17:26:55 -05:00 |
|
irtranslator-readnone-intrinsic-callsite.ll
|
|
|
|
irtranslator-sat.ll
|
GlobalISel: Merge some AMDGPU ABI lowering code to generic code
|
2021-02-18 17:26:55 -05:00 |
|
irtranslator-sibling-call.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-struct-return-intrinsics.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
irtranslator-tail-call.ll
|
AMDGPU/GlobalISel: Implement tail calls
|
2021-05-13 18:57:42 -04:00 |
|
lds-global-non-entry-func.ll
|
[AMDGPU] Rename "LDS lowering" pass name.
|
2021-04-14 20:19:53 +05:30 |
|
lds-global-value.ll
|
[AMDGPU] Increase alignment of LDS globals if necessary before LDS lowering.
|
2021-06-07 18:00:41 +05:30 |
|
lds-misaligned-bug.ll
|
[AMDGPU] Only use ds_read/write_b128 for alignment >= 16
|
2021-04-08 08:12:05 +05:30 |
|
lds-relocs.ll
|
[AMDGPU] Lower kernel LDS into a sorted structure
|
2021-05-25 11:29:29 -07:00 |
|
lds-size.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
lds-zero-initializer.ll
|
MCContext::reportError: don't call report_fatal_error
|
2020-12-20 23:23:12 -08:00 |
|
legalize-add.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-addrspacecast.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-amdgcn.if-invalid.mir
|
AMDGPU/GlobalISel: Tolerate negated control flow intrinsic outputs
|
2020-08-26 08:58:54 -04:00 |
|
legalize-amdgcn.if.xfail.mir
|
|
|
|
legalize-amdgcn.rsq.clamp.mir
|
|
|
|
legalize-amdgcn.wavefrontsize.mir
|
|
|
|
legalize-and.mir
|
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
|
2021-07-09 22:35:00 -07:00 |
|
legalize-anyext.mir
|
|
|
|
legalize-ashr.mir
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
legalize-atomic-cmpxchg-with-success.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomic-cmpxchg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-add.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-and.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-fadd-global.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-fadd-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-max.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-min.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-nand.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-or.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-sub.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-umax.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-umin.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-xchg-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-xchg.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-atomicrmw-xor.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-bitcast.mir
|
GlobalISel: Use unmerge when copying wide vectors to result registers
|
2020-09-24 15:19:51 -04:00 |
|
legalize-bitreverse.mir
|
[AMDGPU] Better codegen for i64 bitreverse
|
2021-02-26 15:51:36 +00:00 |
|
legalize-block-addr.mir
|
|
|
|
legalize-brcond.mir
|
[AMDGPU] Remove fix up operand from SI_ELSE
|
2020-10-20 19:15:21 +09:00 |
|
legalize-bswap.mir
|
GlobalISel: Use unmerge when copying wide vectors to result registers
|
2020-09-24 15:19:51 -04:00 |
|
legalize-build-vector-trunc.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-build-vector.mir
|
|
|
|
legalize-build-vector.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-concat-vectors.mir
|
GlobalISel: Artifact combine unmerge of unmerge
|
2020-09-01 11:01:33 -04:00 |
|
legalize-constant.mir
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
legalize-ctlz-zero-undef.mir
|
|
|
|
legalize-ctlz.mir
|
|
|
|
legalize-ctpop.mir
|
|
|
|
legalize-cttz-zero-undef.mir
|
|
|
|
legalize-cttz.mir
|
|
|
|
legalize-extract-vector-elt.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-extract.mir
|
GlobalISel: Use unmerge when copying wide vectors to result registers
|
2020-09-24 15:19:51 -04:00 |
|
legalize-fabs.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fadd.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fcanonicalize.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fceil.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fcmp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-fconstant.mir
|
|
|
|
legalize-fcopysign.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fcos.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fdiv.mir
|
AMDGPU: Use more accurate fast f64 fdiv
|
2021-01-21 10:51:36 -05:00 |
|
legalize-fexp2.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fexp.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-ffloor.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-flog2.mir
|
|
|
|
legalize-flog10.mir
|
|
|
|
legalize-flog.mir
|
|
|
|
legalize-fma.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fmad.s16.mir
|
|
|
|
legalize-fmad.s32.mir
|
|
|
|
legalize-fmad.s64.mir
|
|
|
|
legalize-fmaxnum.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fminnum.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fmul.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fneg.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fpext.mir
|
GlobalISel: Artifact combine unmerge of unmerge
|
2020-09-01 11:01:33 -04:00 |
|
legalize-fpow.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fpowi.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fptosi.mir
|
[amdgpu] Improve the from f32 to i64.
|
2021-06-19 12:46:48 -04:00 |
|
legalize-fptoui.mir
|
[amdgpu] Improve the from f32 to i64.
|
2021-06-19 12:46:48 -04:00 |
|
legalize-fptrunc.mir
|
|
|
|
legalize-freeze.mir
|
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
|
2021-07-09 22:35:00 -07:00 |
|
legalize-frint.mir
|
|
|
|
legalize-fshl.mir
|
GlobalISel: Lower funnel shifts
|
2021-03-23 09:11:17 -04:00 |
|
legalize-fshr.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fsin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fsqrt.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-fsub.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-icmp.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-implicit-def-s1025.mir
|
|
|
|
legalize-implicit-def.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-insert-vector-elt.mir
|
GlobalISel: Preserve memory type when reducing load/store width
|
2021-06-30 17:05:29 -04:00 |
|
legalize-insert.mir
|
AMDGPU/GlobalISel: Use more accurate legality rules for merge/unmerge
|
2020-08-25 09:40:20 -04:00 |
|
legalize-intrinsic-amdgcn-fdiv-fast.mir
|
|
|
|
legalize-intrinsic-round.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-intrinsic-trunc.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-inttoptr.mir
|
|
|
|
legalize-jump-table.mir
|
|
|
|
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.dim.a16.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.load.2d.d16.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.load.2d.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.load.3d.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.image.sample.a16.ll
|
[AMDGPU] Add maximum NSA size limit ISA feature
|
2021-07-23 16:16:06 +09:00 |
|
legalize-llvm.amdgcn.image.sample.g16.ll
|
[AMDGPU] Add maximum NSA size limit ISA feature
|
2021-07-23 16:16:06 +09:00 |
|
legalize-llvm.amdgcn.image.store.2d.d16.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-llvm.amdgcn.s.buffer.load.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-load-constant-32bit.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-load-constant.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-load-flat.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-load-global.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-load-local.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-load-memory-metadata.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-load-private.mir
|
AMDGPU/GlobalISel: Fix wrong addrspace in test MMOs
|
2021-07-27 15:56:41 -04:00 |
|
legalize-lshr.mir
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
legalize-merge-values-build-vector.mir
|
AMDGPU/GlobalISel: re-auto-generate some test checks
|
2020-08-25 15:54:22 +01:00 |
|
legalize-merge-values.mir
|
|
|
|
legalize-mul.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-or.mir
|
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
|
2021-07-09 22:35:00 -07:00 |
|
legalize-phi.mir
|
GlobalISel: Use unmerge when copying wide vectors to result registers
|
2020-09-24 15:19:51 -04:00 |
|
legalize-ptr-add.mir
|
|
|
|
legalize-ptrmask.mir
|
|
|
|
legalize-ptrtoint.mir
|
|
|
|
legalize-sadde.mir
|
[GlobalISel] Implement widenScalar for carry-in add/sub
|
2021-01-28 17:06:24 -05:00 |
|
legalize-saddo.mir
|
[GlobalISel] Add sext(constant) -> constant artifact combine.
|
2021-02-03 14:10:08 -08:00 |
|
legalize-saddsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-sbfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
legalize-sdiv.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-select.mir
|
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
|
2021-07-09 22:35:00 -07:00 |
|
legalize-sext-inreg.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-sext.mir
|
|
|
|
legalize-sextload-constant-32bit.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-sextload-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-sextload-global.mir
|
GlobalISel: Handle lowering non-power-of-2 extloads
|
2021-07-14 11:54:11 -04:00 |
|
legalize-sextload-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-sextload-private.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-shl.mir
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
legalize-shuffle-vector.mir
|
|
|
|
legalize-shuffle-vector.s16.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-sitofp.mir
|
|
|
|
legalize-smax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-smin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-smulh.mir
|
[GlobalISel][AMDGPU] Lower G_SMULH/G_UMULH
|
2020-09-23 22:25:29 -04:00 |
|
legalize-smulo.mir
|
[GlobalISel][AMDGPU] Lower G_UMULO/G_SMULO
|
2021-03-23 05:45:43 +00:00 |
|
legalize-srem.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-sshlsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-ssube.mir
|
[GlobalISel] Implement widenScalar for carry-in add/sub
|
2021-01-28 17:06:24 -05:00 |
|
legalize-ssubo.mir
|
[GlobalISel] Add sext(constant) -> constant artifact combine.
|
2021-02-03 14:10:08 -08:00 |
|
legalize-ssubsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-store-global.mir
|
GlobalISel: Preserve LLT when bitcasting loads and stores
|
2021-07-19 11:30:14 -04:00 |
|
legalize-store.mir
|
AMDGPU/GlobalISel: Add a few tests for unaligned truncating stores
|
2021-07-27 15:56:41 -04:00 |
|
legalize-sub.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-trunc.mir
|
AMDGPU/GlobalISel: Fix using unlegalizable values in tests
|
2020-08-25 09:39:32 -04:00 |
|
legalize-uadde.mir
|
[GlobalISel] Implement widenScalar for carry-in add/sub
|
2021-01-28 17:06:24 -05:00 |
|
legalize-uaddo.mir
|
Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method""
|
2021-01-25 16:22:22 -08:00 |
|
legalize-uaddsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-ubfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
legalize-udiv.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-uitofp.mir
|
|
|
|
legalize-umax.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-umin.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-umulh.mir
|
GlobalISel: Use unmerge when copying wide vectors to result registers
|
2020-09-24 15:19:51 -04:00 |
|
legalize-umulo.mir
|
[GlobalISel][AMDGPU] Lower G_UMULO/G_SMULO
|
2021-03-23 05:45:43 +00:00 |
|
legalize-unmerge-values.mir
|
[AMDGPU] Fix inconsistent ---/... in MIR tests and regenerate checks
|
2021-04-30 14:10:50 +01:00 |
|
legalize-urem.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-ushlsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-usube.mir
|
[GlobalISel] Implement widenScalar for carry-in add/sub
|
2021-01-28 17:06:24 -05:00 |
|
legalize-usubo.mir
|
Revert "Revert "[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method""
|
2021-01-25 16:22:22 -08:00 |
|
legalize-usubsat.mir
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
legalize-xor.mir
|
[GlobalISel] Add a new artifact combiner for unmerge which looks through general artifact expressions.
|
2021-07-09 22:35:00 -07:00 |
|
legalize-zext.mir
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
legalize-zextload-constant-32bit.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-zextload-flat.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-zextload-global.mir
|
AMDGPU/GlobalISel: Fix incorrect memory types in test
|
2021-07-15 19:11:40 -04:00 |
|
legalize-zextload-local.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
legalize-zextload-private.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.abs.ll
|
[AMDGPU][GlobalISel] Legalize G_ABS
|
2021-06-04 14:46:43 +02:00 |
|
llvm.amdgcn.atomic.dec.ll
|
[AMDGPU] Fix flags of V_MOV_B64_PSEUDO
|
2021-07-09 12:49:28 -07:00 |
|
llvm.amdgcn.atomic.inc.ll
|
[AMDGPU] Fix flags of V_MOV_B64_PSEUDO
|
2021-07-09 12:49:28 -07:00 |
|
llvm.amdgcn.ballot.i32.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.ballot.i64.ll
|
|
|
|
llvm.amdgcn.dispatch.id.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
llvm.amdgcn.dispatch.ptr.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
llvm.amdgcn.div.fmas.ll
|
AMDGPU: Use kill instruction to hint soft clause live ranges
|
2021-02-26 18:26:40 -05:00 |
|
llvm.amdgcn.div.scale.ll
|
[AMDGPU] Update subtarget features for new target ID support
|
2021-01-26 11:25:51 -08:00 |
|
llvm.amdgcn.ds.append.ll
|
|
|
|
llvm.amdgcn.ds.consume.ll
|
|
|
|
llvm.amdgcn.ds.fadd.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.ds.fmax.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.ds.fmin.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.ds.gws.barrier.ll
|
|
|
|
llvm.amdgcn.ds.gws.init.ll
|
|
|
|
llvm.amdgcn.ds.gws.sema.br.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.ds.gws.sema.release.all.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.ds.gws.sema.v.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.ds.ordered.add.gfx10.ll
|
|
|
|
llvm.amdgcn.ds.ordered.add.ll
|
|
|
|
llvm.amdgcn.ds.ordered.swap.ll
|
|
|
|
llvm.amdgcn.end.cf.i32.ll
|
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
|
2021-03-05 11:05:37 +01:00 |
|
llvm.amdgcn.end.cf.i64.ll
|
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
|
2021-03-05 11:05:37 +01:00 |
|
llvm.amdgcn.fdot2.ll
|
[AMDGPU][GlobalISel] Avoid selecting S_PACK with constants
|
2021-01-20 11:54:53 +01:00 |
|
llvm.amdgcn.fmul.legacy.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.global.atomic.csub.ll
|
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
|
2021-06-30 11:45:38 -07:00 |
|
llvm.amdgcn.global.atomic.fadd-with-ret.ll
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
llvm.amdgcn.global.atomic.fadd.ll
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
llvm.amdgcn.icmp.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.if.break.i32.ll
|
[AMDGPU] Add volatile support to SIMemoryLegalizer
|
2021-01-09 00:52:33 +00:00 |
|
llvm.amdgcn.if.break.i64.ll
|
[AMDGPU] Add volatile support to SIMemoryLegalizer
|
2021-01-09 00:52:33 +00:00 |
|
llvm.amdgcn.image.atomic.dim.a16.ll
|
[AMDGPU] Make some VOP3 insts commutable
|
2021-04-28 13:59:08 -04:00 |
|
llvm.amdgcn.image.atomic.dim.ll
|
AMDGPU/GlobalISel: Fix selection of image intrinsics with unused return
|
2021-04-29 20:56:03 +02:00 |
|
llvm.amdgcn.image.atomic.dim.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.image.gather4.a16.dim.ll
|
[AMDGPU] Make some VOP3 insts commutable
|
2021-04-28 13:59:08 -04:00 |
|
llvm.amdgcn.image.gather4.dim.ll
|
[AMDGPU] Add maximum NSA size limit ISA feature
|
2021-07-23 16:16:06 +09:00 |
|
llvm.amdgcn.image.gather4.o.dim.ll
|
[AMDGPU] Add maximum NSA size limit ISA feature
|
2021-07-23 16:16:06 +09:00 |
|
llvm.amdgcn.image.getresinfo.a16.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.image.getresinfo.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.image.load.1d.d16.ll
|
[AMDGPU][GlobalISel] Run SIAddImgInit
|
2021-01-21 15:54:54 +00:00 |
|
llvm.amdgcn.image.load.1d.ll
|
[AMDGPU] Add some image tests with enable-prt-strict-null disabled. NFC.
|
2021-03-31 17:27:20 +01:00 |
|
llvm.amdgcn.image.load.2d.ll
|
[AMDGPU][GlobalISel] Run SIAddImgInit
|
2021-01-21 15:54:54 +00:00 |
|
llvm.amdgcn.image.load.2darraymsaa.a16.ll
|
[AMDGPU][GlobalISel] Run SIAddImgInit
|
2021-01-21 15:54:54 +00:00 |
|
llvm.amdgcn.image.load.2darraymsaa.ll
|
[AMDGPU][GlobalISel] Run SIAddImgInit
|
2021-01-21 15:54:54 +00:00 |
|
llvm.amdgcn.image.load.3d.a16.ll
|
[AMDGPU][GlobalISel] Run SIAddImgInit
|
2021-01-21 15:54:54 +00:00 |
|
llvm.amdgcn.image.load.3d.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.image.sample.g16.ll
|
[AMDGPU] Add maximum NSA size limit ISA feature
|
2021-07-23 16:16:06 +09:00 |
|
llvm.amdgcn.image.sample.ltolz.a16.ll
|
[AMDGPU] Make some VOP3 insts commutable
|
2021-04-28 13:59:08 -04:00 |
|
llvm.amdgcn.image.sample.ltolz.ll
|
Revert "[AMDGPU] Insert waitcnt after returning from call"
|
2020-09-23 17:16:39 +02:00 |
|
llvm.amdgcn.image.store.2d.d16.ll
|
[AMDGPU] Update subtarget features for new target ID support
|
2021-01-26 11:25:51 -08:00 |
|
llvm.amdgcn.image.store.2d.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.implicit.buffer.ptr.ll
|
|
|
|
llvm.amdgcn.init.exec.ll
|
|
|
|
llvm.amdgcn.init.exec.wave32.ll
|
|
|
|
llvm.amdgcn.interp.p1.f16.ll
|
|
|
|
llvm.amdgcn.intersect_ray.ll
|
Reland "[AMDGPU] Add gfx1013 target"
|
2021-06-08 21:15:35 -04:00 |
|
llvm.amdgcn.is.private.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.is.shared.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.kernarg.segment.ptr.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.mov.dpp8.ll
|
|
|
|
llvm.amdgcn.mov.dpp.ll
|
[AMDGPU][MC] Corrected bound_ctrl for compatibility with sp3
|
2021-02-22 14:59:40 +03:00 |
|
llvm.amdgcn.permlane.ll
|
|
|
|
llvm.amdgcn.queue.ptr.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
llvm.amdgcn.raw.buffer.atomic.add.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
llvm.amdgcn.raw.buffer.atomic.fadd.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.load.format.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.load.format.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.store.format.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.store.format.f32.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.buffer.store.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.tbuffer.load.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.tbuffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.tbuffer.store.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.tbuffer.store.i8.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.raw.tbuffer.store.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.rsq.clamp.ll
|
|
|
|
llvm.amdgcn.s.buffer.load.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
llvm.amdgcn.s.setreg.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.s.sleep.ll
|
|
|
|
llvm.amdgcn.sbfe.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
llvm.amdgcn.sdot2.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.sdot4.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.sdot8.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.set.inactive.ll
|
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect
|
2021-03-05 11:05:37 +01:00 |
|
llvm.amdgcn.softwqm.ll
|
|
|
|
llvm.amdgcn.struct.buffer.atomic.add.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
llvm.amdgcn.struct.buffer.atomic.fadd.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.load.format.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.load.format.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.store.format.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.store.format.f32.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.buffer.store.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.tbuffer.load.f16.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.struct.tbuffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
llvm.amdgcn.trig.preop.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
llvm.amdgcn.ubfe.ll
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
llvm.amdgcn.udot2.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.udot4.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.udot8.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.update.dpp.ll
|
AMDGPU: Use kill instruction to hint soft clause live ranges
|
2021-02-26 18:26:40 -05:00 |
|
llvm.amdgcn.workgroup.id.ll
|
[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
|
llvm.amdgcn.workitem.id.ll
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
llvm.amdgcn.wqm.demote.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
llvm.amdgcn.wqm.ll
|
|
|
|
llvm.amdgcn.wqm.vote.ll
|
|
|
|
llvm.amdgcn.writelane.ll
|
[AMDGPU] Stop adding an implicit def of vcc_hi for wave32
|
2020-12-02 10:11:42 +00:00 |
|
llvm.amdgcn.wwm.ll
|
[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
|
2021-03-03 09:33:57 +01:00 |
|
llvm.powi.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
llvm.trap.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
load-constant.96.ll
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
load-local.96.ll
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
load-local.128.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
load-unaligned.ll
|
GlobalISel: Avoid use of G_INSERT in insertParts
|
2021-06-08 14:44:24 -04:00 |
|
localizer.ll
|
AMDGPU: Use kill instruction to hint soft clause live ranges
|
2021-02-26 18:26:40 -05:00 |
|
lshr.ll
|
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
|
memory-legalizer-atomic-fence.ll
|
AMDGPU: Update AMDHSA code object version handling
|
2020-10-14 13:04:27 -04:00 |
|
merge-buffer-stores.ll
|
[AMDGPU][GlobalISel] Handle G_PTR_ADD when looking for constant offset
|
2021-01-28 11:20:09 +01:00 |
|
minmaxabs.ll
|
|
|
|
mubuf-global.ll
|
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
|
2021-06-30 11:45:38 -07:00 |
|
mul.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
|
mul.v2i16.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
|
no-cse-nonlocal-convergent-instrs.mir
|
[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent instrs
|
2021-05-05 14:22:03 -07:00 |
|
no-legalize-atomic.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
non-entry-alloca.ll
|
[AMDGPU] Init scratch only if necessary
|
2021-07-14 10:45:22 +02:00 |
|
orn2.ll
|
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
|
postlegalizer-combiner-divrem.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizercombiner-and.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
postlegalizercombiner-sbfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
postlegalizercombiner-select.mir
|
[GlobalISel] Add X,Y<dead> = G_UNMERGE Z -> X = G_TRUNC Z
|
2020-09-14 17:27:23 -07:00 |
|
postlegalizercombiner-ubfx.mir
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
prelegalizer-combiner-divrem.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
prelegalizer-combiner-memcpy-inline.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
read_register.ll
|
|
|
|
readcyclecounter.ll
|
[AMDGPU] Add some GFX10.3 testing. NFC.
|
2021-05-11 11:21:19 +01:00 |
|
regbankcombiner-smed3.mir
|
AMDGPU/GlobalISel: Add integer med3 combines
|
2021-04-27 11:52:23 +02:00 |
|
regbankcombiner-umed3.mir
|
AMDGPU/GlobalISel: Add integer med3 combines
|
2021-04-27 11:52:23 +02:00 |
|
regbankselect-add.s16.mir
|
|
|
|
regbankselect-add.s32.mir
|
|
|
|
regbankselect-add.v2s16.mir
|
|
|
|
regbankselect-amdgcn-exp-compr.mir
|
|
|
|
regbankselect-amdgcn-exp.mir
|
|
|
|
regbankselect-amdgcn-s-buffer-load.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-amdgcn.ballot.i64.mir
|
AMDGPU/GlobalISel: Fix using readfirstlane with ballot intrinsics
|
2020-08-17 09:53:25 -04:00 |
|
regbankselect-amdgcn.class.mir
|
|
|
|
regbankselect-amdgcn.cvt.pkrtz.mir
|
|
|
|
regbankselect-amdgcn.div.fmas.mir
|
|
|
|
regbankselect-amdgcn.div.scale.mir
|
|
|
|
regbankselect-amdgcn.ds.append.mir
|
|
|
|
regbankselect-amdgcn.ds.bpermute.mir
|
|
|
|
regbankselect-amdgcn.ds.consume.mir
|
|
|
|
regbankselect-amdgcn.ds.gws.init.mir
|
|
|
|
regbankselect-amdgcn.ds.gws.sema.v.mir
|
|
|
|
regbankselect-amdgcn.ds.ordered.add.mir
|
|
|
|
regbankselect-amdgcn.ds.ordered.swap.mir
|
|
|
|
regbankselect-amdgcn.ds.permute.mir
|
|
|
|
regbankselect-amdgcn.ds.swizzle.mir
|
|
|
|
regbankselect-amdgcn.else.32.mir
|
|
|
|
regbankselect-amdgcn.else.64.mir
|
|
|
|
regbankselect-amdgcn.fcmp.mir
|
|
|
|
regbankselect-amdgcn.fmul.legacy.mir
|
|
|
|
regbankselect-amdgcn.groupstaticsize.mir
|
|
|
|
regbankselect-amdgcn.icmp.mir
|
|
|
|
regbankselect-amdgcn.image.load.1d.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-amdgcn.image.sample.1d.ll
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-amdgcn.interp.mov.mir
|
|
|
|
regbankselect-amdgcn.interp.p1.f16.mir
|
|
|
|
regbankselect-amdgcn.interp.p1.mir
|
|
|
|
regbankselect-amdgcn.interp.p2.f16.mir
|
|
|
|
regbankselect-amdgcn.interp.p2.mir
|
|
|
|
regbankselect-amdgcn.kernarg.segment.ptr.mir
|
|
|
|
regbankselect-amdgcn.kill.mir
|
|
|
|
regbankselect-amdgcn.live.mask.mir
|
[AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic
|
2021-02-15 08:45:46 +09:00 |
|
regbankselect-amdgcn.mfma.gfx90a.mir
|
[AMDGPU] gfx90a support
|
2021-02-17 16:01:32 -08:00 |
|
regbankselect-amdgcn.mfma.mir
|
|
|
|
regbankselect-amdgcn.ps.live.mir
|
|
|
|
regbankselect-amdgcn.raw.buffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
regbankselect-amdgcn.readfirstlane.mir
|
|
|
|
regbankselect-amdgcn.readlane.mir
|
AMDGPU/GlobalISel: Handle AGPRs used for SGPR operands.
|
2020-08-24 17:54:34 -04:00 |
|
regbankselect-amdgcn.s.buffer.load.ll
|
GlobalISel: Preserve memory type when reducing load/store width
|
2021-06-30 17:05:29 -04:00 |
|
regbankselect-amdgcn.s.buffer.load.mir
|
CodeGen: Print/parse LLTs in MachineMemOperands
|
2021-06-30 16:54:13 -04:00 |
|
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
|
|
|
|
regbankselect-amdgcn.s.getpc.mir
|
|
|
|
regbankselect-amdgcn.s.getreg.mir
|
|
|
|
regbankselect-amdgcn.s.memrealtime.mir
|
|
|
|
regbankselect-amdgcn.s.memtime.mir
|
|
|
|
regbankselect-amdgcn.s.sendmsg.mir
|
|
|
|
regbankselect-amdgcn.s.sendmsghalt.mir
|
|
|
|
regbankselect-amdgcn.struct.buffer.load.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
|
regbankselect-amdgcn.struct.buffer.store.ll
|
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
|
2021-07-26 14:27:30 +01:00 |
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regbankselect-amdgcn.update.dpp.mir
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regbankselect-amdgcn.wqm.demote.mir
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[AMDGPU] Add llvm.amdgcn.wqm.demote intrinsic
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2021-02-15 08:45:46 +09:00 |
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regbankselect-amdgcn.wqm.mir
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regbankselect-amdgcn.wqm.vote.mir
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regbankselect-amdgcn.writelane.mir
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regbankselect-amdgcn.wwm.mir
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[AMDGPU] Rename amdgcn_wwm to amdgcn_strict_wwm
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2021-03-03 09:33:57 +01:00 |
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regbankselect-amdgpu-ffbh-u32.mir
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regbankselect-and-s1.mir
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regbankselect-and.mir
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regbankselect-anyext.mir
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regbankselect-ashr.mir
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[AMDGPU][GlobalISel] Fix v2s16 right shifts
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2021-02-04 17:04:32 +00:00 |
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regbankselect-atomic-cmpxchg.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-add.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-and.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-fadd.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-max.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-min.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-or.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-sub.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-umax.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-umin.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-xchg.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-atomicrmw-xor.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-bitcast.mir
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regbankselect-bitreverse.mir
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[AMDGPU] Better codegen for i64 bitreverse
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2021-02-26 15:51:36 +00:00 |
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regbankselect-block-addr.mir
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regbankselect-brcond.mir
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regbankselect-bswap.mir
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regbankselect-build-vector-trunc.mir
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regbankselect-build-vector-trunc.v2s16.mir
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regbankselect-build-vector.mir
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AMDGPU/GlobalISel: Fix missing 256-bit AGPR mapping
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2020-08-17 09:53:26 -04:00 |
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regbankselect-concat-vector.mir
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regbankselect-constant.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-copy.mir
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regbankselect-ctlz-zero-undef.mir
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regbankselect-ctpop.mir
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regbankselect-cttz-zero-undef.mir
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regbankselect-default.mir
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AMDGPU/GlobalISel: re-auto-generate some test checks
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2020-08-25 15:54:22 +01:00 |
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regbankselect-dyn-stackalloc.mir
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regbankselect-extract-vector-elt.mir
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regbankselect-extract.mir
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regbankselect-fabs.mir
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regbankselect-fadd.mir
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regbankselect-fcanonicalize.mir
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regbankselect-fceil.mir
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regbankselect-fcmp.mir
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regbankselect-fexp2.mir
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regbankselect-flog2.mir
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regbankselect-fma.mir
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regbankselect-fmul.mir
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regbankselect-fneg.mir
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regbankselect-fpext.mir
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regbankselect-fptosi.mir
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regbankselect-fptoui.mir
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regbankselect-fptrunc.mir
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regbankselect-frame-index.mir
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regbankselect-freeze.mir
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regbankselect-frint.mir
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regbankselect-fshr.mir
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regbankselect-fsqrt.mir
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regbankselect-fsub.mir
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regbankselect-icmp.mir
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regbankselect-icmp.s16.mir
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regbankselect-illegal-copy.mir
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regbankselect-insert-vector-elt.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-insert.mir
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regbankselect-intrinsic-trunc.mir
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regbankselect-inttoptr.mir
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regbankselect-load.mir
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GlobalISel: Preserve memory type when reducing load/store width
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2021-06-30 17:05:29 -04:00 |
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regbankselect-lshr.mir
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[AMDGPU][GlobalISel] Fix v2s16 right shifts
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2021-02-04 17:04:32 +00:00 |
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regbankselect-merge-values.mir
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regbankselect-mul.mir
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regbankselect-or.mir
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regbankselect-phi-s1.mir
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regbankselect-phi.mir
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regbankselect-ptr-add.mir
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regbankselect-ptrmask.mir
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regbankselect-ptrtoint.mir
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regbankselect-reg-sequence.mir
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regbankselect-sadde.mir
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regbankselect-sbfx.mir
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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regbankselect-select.mir
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regbankselect-sext-inreg.mir
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regbankselect-sext.mir
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regbankselect-sextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-shl.mir
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regbankselect-shuffle-vector.mir
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regbankselect-sitofp.mir
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regbankselect-smax.mir
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[AMDGPU][GlobalISel] Use scalar min/max instructions
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2021-02-04 17:04:32 +00:00 |
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regbankselect-smin.mir
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[AMDGPU][GlobalISel] Use scalar min/max instructions
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2021-02-04 17:04:32 +00:00 |
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regbankselect-smulh.mir
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regbankselect-split-scalar-load-metadata.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-ssube.mir
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regbankselect-sub.mir
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regbankselect-trunc.mir
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regbankselect-uadde.mir
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regbankselect-uaddo.mir
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regbankselect-ubfx.mir
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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regbankselect-uitofp.mir
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regbankselect-umax.mir
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[AMDGPU][GlobalISel] Use scalar min/max instructions
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2021-02-04 17:04:32 +00:00 |
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regbankselect-umin.mir
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[AMDGPU][GlobalISel] Use scalar min/max instructions
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2021-02-04 17:04:32 +00:00 |
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regbankselect-umulh.mir
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regbankselect-uniform-load-noclobber.mir
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GlobalISel: Preserve memory type when reducing load/store width
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2021-06-30 17:05:29 -04:00 |
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regbankselect-unmerge-values.mir
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regbankselect-usube.mir
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regbankselect-usubo.mir
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regbankselect-waterfall-agpr.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-widen-scalar-loads.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect-xor.mir
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regbankselect-zext.mir
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regbankselect-zextload.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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regbankselect.mir
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CodeGen: Print/parse LLTs in MachineMemOperands
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2021-06-30 16:54:13 -04:00 |
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ret.ll
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roundeven.ll
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[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
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2021-06-30 11:45:38 -07:00 |
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saddsat.ll
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[GlobalISel] Add a constant folding combine.
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2021-07-26 14:53:33 -07:00 |
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sbfx.ll
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
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2021-06-28 09:06:44 -04:00 |
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sdiv.i32.ll
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[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
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sdiv.i64.ll
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[AMDGPU] Improve killed check for vgpr optimization
|
2021-07-21 15:24:59 +02:00 |
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sdivrem.ll
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GlobalISel: Use LLT in memory legality queries
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2021-06-30 17:44:13 -04:00 |
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shader-epilogs.ll
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shl-ext-reduce.ll
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[GISel] Eliminate redundant bitmasking
|
2021-06-17 12:53:00 -07:00 |
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shl.ll
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GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
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shlN_add.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
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smed3.ll
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AMDGPU/GlobalISel: Add integer med3 combines
|
2021-04-27 11:52:23 +02:00 |
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smrd.ll
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[NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
|
2021-01-05 12:57:17 -08:00 |
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srem.i32.ll
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[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
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srem.i64.ll
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[AMDGPU] Improve killed check for vgpr optimization
|
2021-07-21 15:24:59 +02:00 |
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ssubsat.ll
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[GlobalISel] Add a constant folding combine.
|
2021-07-26 14:53:33 -07:00 |
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store-local.96.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
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store-local.128.ll
|
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts
|
2021-04-26 17:21:49 -04:00 |
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trunc.ll
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uaddsat.ll
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[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
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ubfx.ll
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
udiv.i32.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
udiv.i64.ll
|
[AMDGPU] Improve killed check for vgpr optimization
|
2021-07-21 15:24:59 +02:00 |
|
udivrem.ll
|
GlobalISel: Use LLT in memory legality queries
|
2021-06-30 17:44:13 -04:00 |
|
umed3.ll
|
AMDGPU/GlobalISel: Add integer med3 combines
|
2021-04-27 11:52:23 +02:00 |
|
urem.i32.ll
|
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
|
2021-07-27 11:27:58 +01:00 |
|
urem.i64.ll
|
[AMDGPU] Improve killed check for vgpr optimization
|
2021-07-21 15:24:59 +02:00 |
|
usubsat.ll
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
widen-i8-i16-scalar-loads.ll
|
[AMDGPU][GlobalISel] Widen 1 and 2 byte scalar loads
|
2021-05-05 15:18:19 -07:00 |
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write_register.ll
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xnor.ll
|
GlobalISel: Use DAG call lowering infrastructure in a more compatible way
|
2021-05-05 17:35:02 -04:00 |
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zextload.ll
|
[AMDGPU] Extend gfx10 test coverage. NFC.
|
2021-03-29 11:13:55 +02:00 |
