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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
88 lines
2.1 KiB
LLVM
88 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s --check-prefix=LNX1
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; RUN: llc < %s -mtriple=x86_64-linux-gnux32 | FileCheck %s --check-prefix=LNX2
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; RUN: llc < %s -mtriple=x86_64-nacl | FileCheck %s --check-prefix=NACL
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; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=WIN
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define i64 @test2(i64 %a) {
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; LNX1-LABEL: test2:
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; LNX1: # %bb.0:
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; LNX1-NEXT: leaq (,%rdi,4), %rax
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; LNX1-NEXT: orq %rdi, %rax
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; LNX1-NEXT: retq
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;
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; LNX2-LABEL: test2:
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; LNX2: # %bb.0:
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; LNX2-NEXT: leaq (,%rdi,4), %rax
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; LNX2-NEXT: orq %rdi, %rax
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; LNX2-NEXT: retq
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;
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; NACL-LABEL: test2:
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; NACL: # %bb.0:
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; NACL-NEXT: leaq (,%rdi,4), %rax
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; NACL-NEXT: orq %rdi, %rax
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; NACL-NEXT: retq
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;
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; WIN-LABEL: test2:
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; WIN: # %bb.0:
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; WIN-NEXT: leaq (,%rcx,4), %rax
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; WIN-NEXT: orq %rcx, %rax
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; WIN-NEXT: retq
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%tmp2 = shl i64 %a, 2
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%tmp3 = or i64 %tmp2, %a
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ret i64 %tmp3
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}
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define i32 @test(i32 %a) {
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; LNX1-LABEL: test:
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; LNX1: # %bb.0:
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; LNX1-NEXT: # kill: def $edi killed $edi def $rdi
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; LNX1-NEXT: leal (%rdi,%rdi,2), %eax
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; LNX1-NEXT: retq
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;
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; LNX2-LABEL: test:
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; LNX2: # %bb.0:
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; LNX2-NEXT: # kill: def $edi killed $edi def $rdi
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; LNX2-NEXT: leal (%rdi,%rdi,2), %eax
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; LNX2-NEXT: retq
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;
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; NACL-LABEL: test:
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; NACL: # %bb.0:
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; NACL-NEXT: # kill: def $edi killed $edi def $rdi
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; NACL-NEXT: leal (%rdi,%rdi,2), %eax
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; NACL-NEXT: retq
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;
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; WIN-LABEL: test:
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; WIN: # %bb.0:
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; WIN-NEXT: # kill: def $ecx killed $ecx def $rcx
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; WIN-NEXT: leal (%rcx,%rcx,2), %eax
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; WIN-NEXT: retq
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%tmp2 = mul i32 %a, 3
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ret i32 %tmp2
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}
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define i64 @test3(i64 %a) {
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; LNX1-LABEL: test3:
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; LNX1: # %bb.0:
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; LNX1-NEXT: leaq (,%rdi,8), %rax
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; LNX1-NEXT: retq
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;
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; LNX2-LABEL: test3:
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; LNX2: # %bb.0:
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; LNX2-NEXT: leaq (,%rdi,8), %rax
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; LNX2-NEXT: retq
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;
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; NACL-LABEL: test3:
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; NACL: # %bb.0:
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; NACL-NEXT: leaq (,%rdi,8), %rax
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; NACL-NEXT: retq
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;
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; WIN-LABEL: test3:
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; WIN: # %bb.0:
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; WIN-NEXT: leaq (,%rcx,8), %rax
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; WIN-NEXT: retq
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%tmp2 = shl i64 %a, 3
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ret i64 %tmp2
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}
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