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4d1b8425dd
not all lakemont MCU support long nop. we can't assume we can generate long nop by default for MCU. Differential Revision: https://reviews.llvm.org/D26895 llvm-svn: 288363
47 lines
1.7 KiB
ArmAsm
47 lines
1.7 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-apple-darwin10.0 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-apple-darwin8 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=slm %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=LNOP7 %s
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# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu -mcpu=lakemont %s | llvm-objdump -d -no-show-raw-insn - | FileCheck --check-prefix=NOP1 %s
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# Ensure alignment directives also emit sequences of 15-byte NOPs on processors
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# capable of using long NOPs.
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inc %eax
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.p2align 5
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inc %eax
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# CHECK: 0: inc
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# CHECK-NEXT: 1: nop
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# CHECK-NEXT: 10: nop
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# CHECK-NEXT: 1f: nop
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# CHECK-NEXT: 20: inc
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# On Silvermont we emit only 7 byte NOPs since longer NOPs are not profitable.
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# LNOP7: 0: inc
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# LNOP7-NEXT: 1: nop
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# LNOP7-NEXT: 8: nop
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# LNOP7-NEXT: f: nop
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# LNOP7-NEXT: 16: nop
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# LNOP7-NEXT: 1d: nop
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# LNOP7-NEXT: 20: inc
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# On Lakemont we emit only 1 byte NOPs since longer NOPs are not supported/legal
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# NOP1: 0: inc
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# NOP1-NEXT: 1: nop
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# NOP1-NEXT: 2: nop
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# NOP1-NEXT: 3: nop
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# NOP1-NEXT: 4: nop
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# NOP1-NEXT: 5: nop
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# NOP1-NEXT: 6: nop
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# .......
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# NOP1: 17: nop
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# NOP1-NEXT: 18: nop
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# NOP1-NEXT: 19: nop
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# NOP1-NEXT: 1a: nop
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# NOP1-NEXT: 1b: nop
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# NOP1-NEXT: 1c: nop
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# NOP1-NEXT: 1d: nop
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# NOP1-NEXT: 1e: nop
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# NOP1-NEXT: 1f: nop
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# NOP1-NEXT: 20: inc
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