Eli Friedman 0af449d2a7 [SelectionDAG] Add an overload of getStepVector that assumes step 1. ... This is mostly a minor convenience, but the pattern seems frequent enough to be worthwhile (and we'll probably add more uses in the future). Differential Revision: https://reviews.llvm.org/D105850		2021-07-14 11:37:01 -07:00
..
AsmParser	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
Disassembler	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
GISel	[AArch64][GlobalISel] Mark v2s64 -> v2p0 G_INTTOPTR as legal	2021-07-13 17:28:14 -07:00
MCTargetDesc	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
TargetInfo
Utils
AArch64.h	[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.	2021-05-07 17:01:27 -07:00
AArch64.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	[AArch64] De-capitalize some Emit* functions	2021-07-11 22:05:39 -07:00
AArch64BranchTargets.cpp	[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.	2021-04-23 10:07:25 +02:00
AArch64CallingConvention.cpp	[clang][AArch64] Correctly align HFA arguments when passed on the stack	2021-04-15 22:58:14 +01:00
AArch64CallingConvention.h
AArch64CallingConvention.td	IR/AArch64/X86: add "swifttailcc" calling convention.	2021-05-17 10:48:34 +01:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64Combine.td	[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX	2021-06-28 09:06:44 -04:00
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp	[AArch64] Fix some coding standard issues related to namespace llvm	2021-05-05 15:27:16 -07:00
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp	IR+AArch64: add a "swiftasync" argument attribute.	2021-05-14 11:43:58 +01:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp	[AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32.	2021-07-12 15:30:42 -07:00
AArch64FrameLowering.cpp	[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)	2021-06-24 18:24:32 +01:00
AArch64FrameLowering.h	[NFC] Fix a few whitespace issues and typos.	2021-07-04 11:49:58 +01:00
AArch64GenRegisterBankInfo.def	AArch64: support i128 cmpxchg in GlobalISel.	2021-05-14 10:41:38 +01:00
AArch64InstrAtomics.td
AArch64InstrFormats.td	[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory	2021-07-06 12:03:54 +00:00
AArch64InstrGISel.td	AArch64: support i128 cmpxchg in GlobalISel.	2021-05-14 10:41:38 +01:00
AArch64InstrInfo.cpp	[AArch64] Dump a little more info about unimplemented reg-to-reg copies. NFC	2021-07-12 15:37:11 -07:00
AArch64InstrInfo.h	[NFC] Fix a few whitespace issues and typos.	2021-07-04 11:49:58 +01:00
AArch64InstrInfo.td	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
AArch64ISelDAGToDAG.cpp	[CodeGen][AArch64][SVE] Use ld1r[bhsd] for vector splat from memory	2021-07-06 12:03:54 +00:00
AArch64ISelLowering.cpp	[SelectionDAG] Add an overload of getStepVector that assumes step 1.	2021-07-14 11:37:01 -07:00
AArch64ISelLowering.h	[AArch64] Sync isDef32 to the current x86 version.	2021-07-06 17:05:01 -07:00
AArch64LoadStoreOptimizer.cpp	Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"	2021-06-23 09:54:16 +03:00
AArch64LowerHomogeneousPrologEpilog.cpp	[CodeGen] Add missing includes (NFC)	2021-06-06 15:48:27 +02:00
AArch64MachineFunctionInfo.cpp	[llvm] Rename StringRef _lower() method calls to _insensitive()	2021-06-25 00:22:01 +03:00
AArch64MachineFunctionInfo.h	IR/AArch64/X86: add "swifttailcc" calling convention.	2021-05-17 10:48:34 +01:00
AArch64MacroFusion.cpp	[AArch64] Fix some coding standard issues related to namespace llvm	2021-05-05 15:27:16 -07:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp	[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local	2021-05-07 09:44:26 -07:00
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp	[NFCI] Move DEBUG_TYPE definition below #includes	2021-05-30 17:31:01 +08:00
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td	AArch64: support i128 cmpxchg in GlobalISel.	2021-05-14 10:41:38 +01:00
AArch64RegisterInfo.cpp	IR/AArch64/X86: add "swifttailcc" calling convention.	2021-05-17 10:48:34 +01:00
AArch64RegisterInfo.h	Change materializeFrameBaseRegister() to return register	2021-01-22 15:51:06 -08:00
AArch64RegisterInfo.td	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
AArch64SchedA53.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedA55.td	[AArch64] Set the latency of Cortex-A55 stores to 1	2021-07-12 13:39:35 +01:00
AArch64SchedA57.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedA57WriteRes.td
AArch64SchedA64FX.td
AArch64SchedCyclone.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedExynosM3.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedExynosM4.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedExynosM5.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedFalkor.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedThunderX3T110.td
AArch64SchedThunderX.td	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SchedTSV110.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp	[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD	2021-02-18 16:55:16 +00:00
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp	[AArch64] reuse another map iterator. NFC	2020-09-28 11:30:21 -07:00
AArch64SLSHardening.cpp	[ARM][AArch64] SLSHardening: make non-comdat thunks possible	2021-05-20 17:07:05 +02:00
AArch64SMEInstrInfo.td	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
AArch64SpeculationHardening.cpp
AArch64StackTagging.cpp	[DebugInfo] Correctly update dbg.values with duplicated location ops	2021-07-14 11:17:24 +01:00
AArch64StackTaggingPreRA.cpp	[AArch64] Fix some coding standard issues related to namespace llvm	2021-05-05 15:27:16 -07:00
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries	2021-06-21 13:00:36 +01:00
AArch64Subtarget.h	[AArch64] Add target features for Armv9-A Scalable Matrix Extension (SME)	2021-07-12 13:28:10 +00:00
AArch64SVEInstrInfo.td	[AArch64][SVE] Add ISel patterns for floating point compare with zero instructions	2021-07-08 10:46:12 +00:00
AArch64SystemOperands.td	[Aarch64] Adding support for Armv9-A Realm Management Extension	2021-06-28 13:45:22 +01:00
AArch64TargetMachine.cpp	Fix typo in help text for -aarch64-enable-branch-targets.	2021-07-05 16:15:40 +01:00
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	[CostModel][AArch64] Make loads/stores of <vscale x 1 x eltty> invalid.	2021-07-14 16:44:22 +01:00
AArch64TargetTransformInfo.h	[TTI] Remove IsPairwiseForm from getArithmeticReductionCost	2021-07-09 11:51:16 +01:00
CMakeLists.txt	[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.	2021-05-07 17:01:27 -07:00
SMEInstrFormats.td	[AArch64][SME] Add matrix register definitions and parsing support	2021-07-14 08:25:49 +00:00
SVEInstrFormats.td	[AArch64][SVE] Add ISel patterns for floating point compare with zero instructions	2021-07-08 10:46:12 +00:00
SVEIntrinsicOpts.cpp	[AArch64] Fix namespace issue. NFC	2021-05-06 11:16:07 -07:00