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443ef62a38
Add VBRD/VMV vector instructions. In order to do that, also support VM512 registers and RV instruction format in MC layer. Also add regression tests for new instructions. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D89641
17 lines
634 B
ArmAsm
17 lines
634 B
ArmAsm
# RUN: llvm-mc -triple=ve --show-encoding < %s \
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# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
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# RUN: | FileCheck %s --check-prefixes=CHECK-INST
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# CHECK-INST: vmv %v11, 23, %v11
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# CHECK-ENCODING: encoding: [0x00,0x0b,0x00,0x0b,0x00,0x17,0x00,0x9c]
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vmv %v11, 23, %v11
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# CHECK-INST: vmv %v11, %s12, %vix, %vm15
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# CHECK-ENCODING: encoding: [0x00,0xff,0x00,0x0b,0x00,0x8c,0x0f,0x9c]
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vmv %v11, %s12, %vix, %vm15
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# CHECK-INST: vmv %vix, 127, %v63
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# CHECK-ENCODING: encoding: [0x00,0x3f,0x00,0xff,0x00,0x7f,0x00,0x9c]
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vmv %vix, 127, %v63, %vm0
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