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llvm-mirror/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
Puyan Lotfi d4c615be8c Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

26 lines
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# RUN: not llc -march=x86-64 -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define void @test(i32* %a) {
entry2:
%b = load i32, i32* %a
%c = add i32 %b, 1
store i32 %c, i32* %a
ret void
}
...
---
name: test
tracksRegLiveness: true
liveins:
- { reg: '$rdi' }
body: |
bb.0.entry2:
liveins: $rdi
; CHECK: [[@LINE+1]]:87: expected ',' before the next machine memory operand
INC32m killed $rdi, 1, _, 0, _, implicit-def dead $eflags :: (store 4 into %ir.a) (load 4 from %ir.a)
RETQ
...