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4bf7d5872e
Upgrade of the IR text tests should be the only thing blocking making typed byval mandatory. Partially done through regex and partially manual.
76 lines
2.2 KiB
LLVM
76 lines
2.2 KiB
LLVM
; RUN: llc -mtriple=thumbv7-apple-ios8.0 %s -o - | FileCheck %s
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; This checks that alignments greater than 4 are respected by APCS
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; targets. Mostly here to make sure *some* correct code is created after some
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; simplifying refactoring; at the time of writing there were no actual APCS
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; users of byval alignments > 4, so no real calls for ABI stability.
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; "byval align 16" can't fit in any regs with an i8* taking up r0.
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define i32 @test_align16(i8*, [4 x i32]* byval([4 x i32]) align 16 %b) {
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; CHECK-LABEL: test_align16:
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; CHECK-NOT: sub sp
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; CHECK: push {r4, r7, lr}
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; CHECK: add r7, sp, #4
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; CHECK: ldr r0, [r7, #8]
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call void @bar()
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%valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
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%val = load i32, i32* %valptr
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ret i32 %val
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}
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; byval align 8 can, but we used to incorrectly set r7 here (miscalculating the
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; space taken up by arg regs).
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define i32 @test_align8(i8*, [4 x i32]* byval([4 x i32]) align 8 %b) {
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; CHECK-LABEL: test_align8:
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; CHECK: sub sp, #8
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; CHECK: push {r4, r7, lr}
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; CHECK: add r7, sp, #4
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; CHECK: strd r2, r3, [r7, #8]
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; CHECK: ldr r0, [r7, #8]
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call void @bar()
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%valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
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%val = load i32, i32* %valptr
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ret i32 %val
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}
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; "byval align 32" can't fit in regs no matter what: it would be misaligned
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; unless the incoming stack was deliberately misaligned.
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define i32 @test_align32(i8*, [4 x i32]* byval([4 x i32]) align 32 %b) {
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; CHECK-LABEL: test_align32:
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; CHECK-NOT: sub sp
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; CHECK: push {r4, r7, lr}
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; CHECK: add r7, sp, #4
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; CHECK: ldr r0, [r7, #8]
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call void @bar()
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%valptr = getelementptr [4 x i32], [4 x i32]* %b, i32 0, i32 0
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%val = load i32, i32* %valptr
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ret i32 %val
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}
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; When passing an object "byval align N", the stack must be at least N-aligned.
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define void @test_call_align16() {
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; CHECK-LABEL: test_call_align16:
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; CHECK: push {r4, r7, lr}
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; CHECK: add r7, sp, #4
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; CHECK: mov [[TMP:r[0-9]+]], sp
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; CHECK: bfc [[TMP]], #0, #4
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; CHECK: mov sp, [[TMP]]
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; While we're here, make sure the caller also puts it at sp
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; CHECK: mov r[[BASE:[0-9]+]], sp
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; CHECK: vst1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r[[BASE]]]
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call i32 @test_align16(i8* null, [4 x i32]* byval([4 x i32]) align 16 @var)
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ret void
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}
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@var = global [4 x i32] zeroinitializer
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declare void @bar()
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