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a9c44b95c0
This new f16 shuffle under Neon would hit an assert in GeneratePerfectShuffle as it would try to treat a f16 vector as an i8. Add f16 handling, treating them like an i16. Differential Revision: https://reviews.llvm.org/D95446
298 lines
10 KiB
LLVM
298 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD
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; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT
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define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_lane_f16_1:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_lane_f16_1:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s0
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <4 x half> %a, i32 1
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_lane_f16_2:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s1
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_lane_f16_2:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s1
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <4 x half> %a, i32 2
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_laneq_f16_6:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s3
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_laneq_f16_6:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s3
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <8 x half> %a, i32 6
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%conv = fpext half %elt to float
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ret float %conv
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}
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define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
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; CHECKHARD-LABEL: test_vget_laneq_f16_7:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtt.f32.f16 s0, s3
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vget_laneq_f16_7:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vcvtt.f32.f16 s0, s3
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%elt = extractelement <8 x half> %a, i32 7
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%conv = fpext half %elt to float
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ret float %conv
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}
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define <4 x half> @insert_v4f16(half %a) {
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; CHECKHARD-LABEL: insert_v4f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $d0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: insert_v4f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov.f16 s0, r0
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%res = insertelement <4 x half> undef, half %a, i32 0
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ret <4 x half> %res
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}
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define <8 x half> @insert_v8f16(half %a) {
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; CHECKHARD-LABEL: insert_v8f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: @ kill: def $s0 killed $s0 def $q0
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: insert_v8f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov.f16 s0, r0
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; CHECKSOFT-NEXT: vmov r2, r3, d1
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%res = insertelement <8 x half> undef, half %a, i32 0
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ret <8 x half> %res
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}
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define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_lane_f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtt.f16.f32 s1, s2
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_lane_f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vmov s2, r2
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s1, s2
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <4 x half> %a, half %b, i32 3
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ret <4 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_1:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtt.f16.f32 s0, s4
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vldr s4, [sp]
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s0, s4
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; CHECKSOFT-NEXT: vmov r2, r3, d1
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 1
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ret <8 x half> %x
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}
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define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
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; CHECKHARD-LABEL: test_vset_laneq_f16_7:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vcvtt.f16.f32 s3, s4
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov d1, r2, r3
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; CHECKSOFT-NEXT: vldr s4, [sp]
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; CHECKSOFT-NEXT: vmov d0, r0, r1
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; CHECKSOFT-NEXT: vcvtt.f16.f32 s3, s4
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; CHECKSOFT-NEXT: vmov r0, r1, d0
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; CHECKSOFT-NEXT: vmov r2, r3, d1
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; CHECKSOFT-NEXT: bx lr
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entry:
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%b = fptrunc float %fb to half
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%x = insertelement <8 x half> %a, half %b, i32 7
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ret <8 x half> %x
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}
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define arm_aapcs_vfpcc <8 x half> @shuffle3step_f16(<32 x half> %src) {
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; CHECKHARD-LABEL: shuffle3step_f16:
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; CHECKHARD: @ %bb.0: @ %entry
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; CHECKHARD-NEXT: vmov r1, s0
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; CHECKHARD-NEXT: vmovx.f16 s12, s1
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; CHECKHARD-NEXT: vmov r0, s12
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; CHECKHARD-NEXT: vext.16 d16, d4, d5, #2
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; CHECKHARD-NEXT: vmovx.f16 s12, s4
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; CHECKHARD-NEXT: vdup.16 q11, d3[1]
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; CHECKHARD-NEXT: vrev32.16 d17, d16
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; CHECKHARD-NEXT: vext.16 d16, d16, d17, #3
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; CHECKHARD-NEXT: vrev32.16 d17, d3
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; CHECKHARD-NEXT: vext.16 d17, d17, d3, #1
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; CHECKHARD-NEXT: vext.16 d16, d16, d17, #2
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; CHECKHARD-NEXT: vext.16 d17, d16, d16, #2
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; CHECKHARD-NEXT: vmov.16 d16[0], r1
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; CHECKHARD-NEXT: vmov.16 d16[1], r0
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; CHECKHARD-NEXT: vmov r0, s3
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; CHECKHARD-NEXT: vmov.16 d16[2], r0
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; CHECKHARD-NEXT: vmov r0, s12
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; CHECKHARD-NEXT: vmovx.f16 s12, s0
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; CHECKHARD-NEXT: vmov r1, s12
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; CHECKHARD-NEXT: vmovx.f16 s12, s3
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; CHECKHARD-NEXT: vmov.16 d16[3], r0
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; CHECKHARD-NEXT: vmov r0, s2
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; CHECKHARD-NEXT: vmov.16 d18[0], r1
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; CHECKHARD-NEXT: vmov r1, s8
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; CHECKHARD-NEXT: vmov.16 d18[1], r0
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; CHECKHARD-NEXT: vmov r0, s12
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; CHECKHARD-NEXT: vmovx.f16 s12, s9
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; CHECKHARD-NEXT: vmov.16 d20[1], r1
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; CHECKHARD-NEXT: vmov.16 d18[2], r0
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; CHECKHARD-NEXT: vmov r0, s5
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; CHECKHARD-NEXT: vmov.16 d18[3], r0
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; CHECKHARD-NEXT: vmov r0, s12
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; CHECKHARD-NEXT: vmov.16 d20[2], r0
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; CHECKHARD-NEXT: vmov r0, s11
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; CHECKHARD-NEXT: vmov.16 d20[3], r0
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; CHECKHARD-NEXT: vmov r0, s10
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; CHECKHARD-NEXT: vext.16 d20, d20, d22, #1
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; CHECKHARD-NEXT: vdup.16 q11, d3[2]
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; CHECKHARD-NEXT: vext.16 d19, d20, d20, #3
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; CHECKHARD-NEXT: vadd.f16 q8, q8, q9
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; CHECKHARD-NEXT: vext.16 d18, d0, d1, #2
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; CHECKHARD-NEXT: vmovx.f16 s0, s8
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; CHECKHARD-NEXT: vmov r1, s0
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; CHECKHARD-NEXT: vmovx.f16 s0, s11
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; CHECKHARD-NEXT: vext.16 d19, d18, d2, #3
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; CHECKHARD-NEXT: vext.16 d18, d2, d18, #1
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; CHECKHARD-NEXT: vext.16 d18, d18, d19, #2
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; CHECKHARD-NEXT: vext.16 d18, d18, d18, #1
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; CHECKHARD-NEXT: vmov.16 d20[1], r1
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; CHECKHARD-NEXT: vmov.16 d20[2], r0
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; CHECKHARD-NEXT: vmov r0, s0
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; CHECKHARD-NEXT: vmov.16 d20[3], r0
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; CHECKHARD-NEXT: vext.16 d20, d20, d22, #1
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; CHECKHARD-NEXT: vext.16 d19, d20, d20, #3
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; CHECKHARD-NEXT: vadd.f16 q0, q8, q9
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; CHECKHARD-NEXT: bx lr
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;
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; CHECKSOFT-LABEL: shuffle3step_f16:
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; CHECKSOFT: @ %bb.0: @ %entry
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; CHECKSOFT-NEXT: vmov r1, s0
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; CHECKSOFT-NEXT: vmovx.f16 s12, s1
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; CHECKSOFT-NEXT: vmov r0, s12
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; CHECKSOFT-NEXT: vext.16 d16, d4, d5, #2
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; CHECKSOFT-NEXT: vmovx.f16 s12, s4
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; CHECKSOFT-NEXT: vdup.16 q11, d3[1]
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; CHECKSOFT-NEXT: vrev32.16 d17, d16
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; CHECKSOFT-NEXT: vext.16 d16, d16, d17, #3
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; CHECKSOFT-NEXT: vrev32.16 d17, d3
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; CHECKSOFT-NEXT: vext.16 d17, d17, d3, #1
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; CHECKSOFT-NEXT: vext.16 d16, d16, d17, #2
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; CHECKSOFT-NEXT: vext.16 d17, d16, d16, #2
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; CHECKSOFT-NEXT: vmov.16 d16[0], r1
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; CHECKSOFT-NEXT: vmov.16 d16[1], r0
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; CHECKSOFT-NEXT: vmov r0, s3
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; CHECKSOFT-NEXT: vmov.16 d16[2], r0
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; CHECKSOFT-NEXT: vmov r0, s12
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; CHECKSOFT-NEXT: vmovx.f16 s12, s0
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; CHECKSOFT-NEXT: vmov r1, s12
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; CHECKSOFT-NEXT: vmovx.f16 s12, s3
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; CHECKSOFT-NEXT: vmov.16 d16[3], r0
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; CHECKSOFT-NEXT: vmov r0, s2
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; CHECKSOFT-NEXT: vmov.16 d18[0], r1
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; CHECKSOFT-NEXT: vmov r1, s8
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; CHECKSOFT-NEXT: vmov.16 d18[1], r0
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; CHECKSOFT-NEXT: vmov r0, s12
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; CHECKSOFT-NEXT: vmovx.f16 s12, s9
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; CHECKSOFT-NEXT: vmov.16 d20[1], r1
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; CHECKSOFT-NEXT: vmov.16 d18[2], r0
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; CHECKSOFT-NEXT: vmov r0, s5
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; CHECKSOFT-NEXT: vmov.16 d18[3], r0
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; CHECKSOFT-NEXT: vmov r0, s12
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; CHECKSOFT-NEXT: vmov.16 d20[2], r0
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; CHECKSOFT-NEXT: vmov r0, s11
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; CHECKSOFT-NEXT: vmov.16 d20[3], r0
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; CHECKSOFT-NEXT: vmov r0, s10
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; CHECKSOFT-NEXT: vext.16 d20, d20, d22, #1
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; CHECKSOFT-NEXT: vdup.16 q11, d3[2]
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; CHECKSOFT-NEXT: vext.16 d19, d20, d20, #3
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; CHECKSOFT-NEXT: vadd.f16 q8, q8, q9
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; CHECKSOFT-NEXT: vext.16 d18, d0, d1, #2
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; CHECKSOFT-NEXT: vmovx.f16 s0, s8
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; CHECKSOFT-NEXT: vmov r1, s0
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; CHECKSOFT-NEXT: vmovx.f16 s0, s11
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; CHECKSOFT-NEXT: vext.16 d19, d18, d2, #3
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; CHECKSOFT-NEXT: vext.16 d18, d2, d18, #1
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; CHECKSOFT-NEXT: vext.16 d18, d18, d19, #2
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; CHECKSOFT-NEXT: vext.16 d18, d18, d18, #1
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; CHECKSOFT-NEXT: vmov.16 d20[1], r1
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; CHECKSOFT-NEXT: vmov.16 d20[2], r0
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; CHECKSOFT-NEXT: vmov r0, s0
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; CHECKSOFT-NEXT: vmov.16 d20[3], r0
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; CHECKSOFT-NEXT: vext.16 d20, d20, d22, #1
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; CHECKSOFT-NEXT: vext.16 d19, d20, d20, #3
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; CHECKSOFT-NEXT: vadd.f16 q0, q8, q9
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; CHECKSOFT-NEXT: bx lr
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entry:
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%s1 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21>
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%s2 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22>
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%s3 = shufflevector <32 x half> %src, <32 x half> undef, <8 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23>
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%a = fadd <8 x half> %s1, %s2
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%r = fadd <8 x half> %a, %s3
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ret <8 x half> %r
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}
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