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The e500 core has a silicon bug that triggers an illegal instruction program trap on any sync other than msync. Other cores will typically ignore illegal sync types, and the documentation even implies that the 'illegal' bits are ignored. Address this hardware deficiency by only using msync, like the PPC440. Differential Revision: https://reviews.llvm.org/D76614
30 lines
788 B
LLVM
30 lines
788 B
LLVM
; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs | FileCheck %s
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=440 | FileCheck %s --check-prefix=PPC440
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=PPC440
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; Fences
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define void @fence_acquire() {
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; CHECK-LABEL: fence_acquire
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; CHECK: lwsync
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; PPC440-NOT: lwsync
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; PPC440: msync
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fence acquire
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ret void
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}
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define void @fence_release() {
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; CHECK-LABEL: fence_release
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; CHECK: lwsync
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; PPC440-NOT: lwsync
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; PPC440: msync
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fence release
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ret void
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}
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define void @fence_seq_cst() {
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; CHECK-LABEL: fence_seq_cst
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; CHECK: sync
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; PPC440: msync
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fence seq_cst
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ret void
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}
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