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4778b6148c
This patch implements the vector string isolate (predicate and non-predicate versions) builtins. The predicate builtins are custom selected within PPCISelDAGToDAG. Differential Revision: https://reviews.llvm.org/D87671
127 lines
3.7 KiB
LLVM
127 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; These test cases aim to test the vector string isolate builtins on Power10.
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declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
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declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
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define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {
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; CHECK-LABEL: test_vclrlb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vclrlb v2, v2, r5
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)
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ret <16 x i8> %tmp
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}
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define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {
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; CHECK-LABEL: test_vclrrb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vclrrb v2, v2, r5
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
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ret <16 x i8> %tmp
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}
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declare <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8>)
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declare <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>)
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declare <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16>)
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declare <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16>)
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declare i32 @llvm.ppc.altivec.vstribr.p(i32, <16 x i8>)
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declare i32 @llvm.ppc.altivec.vstribl.p(i32, <16 x i8>)
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declare i32 @llvm.ppc.altivec.vstrihr.p(i32, <8 x i16>)
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declare i32 @llvm.ppc.altivec.vstrihl.p(i32, <8 x i16>)
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define <16 x i8> @test_vstribr(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribr v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribr(<16 x i8> %a)
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ret <16 x i8> %tmp
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}
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define <16 x i8> @test_vstribl(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribl v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <16 x i8> @llvm.ppc.altivec.vstribl(<16 x i8>%a)
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ret <16 x i8> %tmp
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}
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define <8 x i16> @test_vstrihr(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihr:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihr v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihr(<8 x i16> %a)
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ret <8 x i16> %tmp
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}
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define <8 x i16> @test_vstrihl(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihl:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihl v2, v2
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call <8 x i16> @llvm.ppc.altivec.vstrihl(<8 x i16> %a)
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ret <8 x i16> %tmp
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}
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define i32 @test_vstribr_p(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribr_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribr. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstribr.p(i32 1, <16 x i8> %a)
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ret i32 %tmp
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}
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define i32 @test_vstribl_p(<16 x i8> %a) {
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; CHECK-LABEL: test_vstribl_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstribl. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstribl.p(i32 1, <16 x i8> %a)
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ret i32 %tmp
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}
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define i32 @test_vstrihr_p(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihr_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihr. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstrihr.p(i32 1, <8 x i16> %a)
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ret i32 %tmp
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}
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define i32 @test_vstrihl_p(<8 x i16> %a) {
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; CHECK-LABEL: test_vstrihl_p:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vstrihl. v2, v2
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; CHECK-NEXT: setbc r3, 4*cr6+eq
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; CHECK-NEXT: blr
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entry:
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%tmp = tail call i32 @llvm.ppc.altivec.vstrihl.p(i32 1, <8 x i16> %a)
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ret i32 %tmp
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}
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