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bb10587376
Summary: When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands, it will expose more opportunity for InstiAlias. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D77118
198 lines
6.3 KiB
LLVM
198 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mattr=+vsx -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: vpkuhum v2, v2, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: stfdx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test8i8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuhum v2, v2, v2
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; CHECK-BE-NEXT: stxvd2x v2, 0, r5
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; CHECK-BE-NEXT: ld r4, -16(r1)
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; CHECK-BE-NEXT: std r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <8 x i16>, <8 x i16>* %SrcPtr, align 16
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%1 = trunc <8 x i16> %0 to <8 x i8>
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store <8 x i8> %1, <8 x i8>* %Sink, align 16
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ret void
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}
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define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test4i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: vpkuhum v2, v2, v2
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4i8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuhum v2, v2, v2
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; CHECK-BE-NEXT: stxvw4x v2, 0, r5
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <4 x i16>, <4 x i16>* %SrcPtr, align 16
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%1 = trunc <4 x i16> %0 to <4 x i8>
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store <4 x i8> %1, <4 x i8>* %Sink, align 16
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ret void
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}
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define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test4i8w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r5, r2, .LCPI2_0@toc@ha
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; CHECK-NEXT: lvx v3, 0, r4
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; CHECK-NEXT: addi r5, r5, .LCPI2_0@toc@l
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; CHECK-NEXT: lvx v2, 0, r5
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; CHECK-NEXT: vperm v2, v3, v3, v2
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4i8w:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r4, r5, .LCPI2_0@toc@l
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; CHECK-BE-NEXT: lxvw4x v3, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -16
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; CHECK-BE-NEXT: vperm v2, v2, v2, v3
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; CHECK-BE-NEXT: stxvw4x v2, 0, r4
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
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%1 = trunc <4 x i32> %0 to <4 x i8>
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store <4 x i8> %1, <4 x i8>* %Sink, align 16
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ret void
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}
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define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test2i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: vpkuhum v2, v2, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: mffprd r4, f0
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; CHECK-NEXT: clrldi r4, r4, 48
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; CHECK-NEXT: sth r4, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test2i8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuhum v2, v2, v2
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; CHECK-BE-NEXT: stxvw4x v2, 0, r5
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; CHECK-BE-NEXT: lhz r4, -16(r1)
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; CHECK-BE-NEXT: sth r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <2 x i16>, <2 x i16>* %SrcPtr, align 16
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%1 = trunc <2 x i16> %0 to <2 x i8>
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store <2 x i8> %1, <2 x i8>* %Sink, align 16
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ret void
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}
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define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test4i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: vpkuwum v2, v2, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: stfdx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4i16:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuwum v2, v2, v2
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; CHECK-BE-NEXT: stxvd2x v2, 0, r5
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; CHECK-BE-NEXT: ld r4, -16(r1)
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; CHECK-BE-NEXT: std r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <4 x i32>, <4 x i32>* %SrcPtr, align 16
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%1 = trunc <4 x i32> %0 to <4 x i16>
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store <4 x i16> %1, <4 x i16>* %Sink, align 16
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ret void
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}
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define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test2i16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: vpkuwum v2, v2, v2
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test2i16:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuwum v2, v2, v2
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; CHECK-BE-NEXT: stxvw4x v2, 0, r5
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <2 x i32>, <2 x i32>* %SrcPtr, align 16
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%1 = trunc <2 x i32> %0 to <2 x i16>
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store <2 x i16> %1, <2 x i16>* %Sink, align 16
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ret void
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}
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define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test2i16d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxvd2x vs0, 0, r4
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; CHECK-NEXT: addis r5, r2, .LCPI6_0@toc@ha
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; CHECK-NEXT: addi r4, r5, .LCPI6_0@toc@l
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; CHECK-NEXT: lvx v3, 0, r4
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: vperm v2, v2, v2, v3
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test2i16d:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r4, r5, .LCPI6_0@toc@l
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; CHECK-BE-NEXT: lxvw4x v3, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -16
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; CHECK-BE-NEXT: vperm v2, v2, v2, v3
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; CHECK-BE-NEXT: stxvw4x v2, 0, r4
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <2 x i64>, <2 x i64>* %SrcPtr, align 16
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%1 = trunc <2 x i64> %0 to <2 x i16>
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store <2 x i16> %1, <2 x i16>* %Sink, align 16
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ret void
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}
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