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3dd84ac1da
We will emit these permuted nodes on all VSX little endian subtargets but don't have the patterns available to match them on subtargets that don't have direct moves. Fixes: https://bugs.llvm.org/show_bug.cgi?id=47916
260 lines
8.9 KiB
LLVM
260 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=P9
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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
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; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
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; RUN: -check-prefix=P8
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define dso_local void @test(<2 x double>* nocapture %c, double* nocapture readonly %a) local_unnamed_addr {
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; P9-LABEL: test:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r4, r4, 24
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; P9-NEXT: lxvdsx vs0, 0, r4
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; P9-NEXT: stxv vs0, 0(r3)
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; P9-NEXT: blr
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;
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; P8-LABEL: test:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addi r4, r4, 24
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; P8-NEXT: lxvdsx vs0, 0, r4
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; P8-NEXT: stxvd2x vs0, 0, r3
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; P8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds double, double* %a, i64 3
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%0 = load double, double* %arrayidx, align 8
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%splat.splatinsert.i = insertelement <2 x double> undef, double %0, i32 0
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%splat.splat.i = shufflevector <2 x double> %splat.splatinsert.i, <2 x double> undef, <2 x i32> zeroinitializer
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store <2 x double> %splat.splat.i, <2 x double>* %c, align 16
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ret void
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}
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define dso_local void @test2(<4 x float>* nocapture %c, float* nocapture readonly %a) local_unnamed_addr {
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; P9-LABEL: test2:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r4, r4, 12
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; P9-NEXT: lxvwsx vs0, 0, r4
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; P9-NEXT: stxv vs0, 0(r3)
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; P9-NEXT: blr
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;
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; P8-LABEL: test2:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addi r4, r4, 12
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; P8-NEXT: lfiwzx f0, 0, r4
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; P8-NEXT: xxspltw v2, vs0, 1
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; P8-NEXT: stvx v2, 0, r3
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; P8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds float, float* %a, i64 3
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%0 = load float, float* %arrayidx, align 4
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%splat.splatinsert.i = insertelement <4 x float> undef, float %0, i32 0
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%splat.splat.i = shufflevector <4 x float> %splat.splatinsert.i, <4 x float> undef, <4 x i32> zeroinitializer
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store <4 x float> %splat.splat.i, <4 x float>* %c, align 16
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ret void
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}
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define dso_local void @test3(<4 x i32>* nocapture %c, i32* nocapture readonly %a) local_unnamed_addr {
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; P9-LABEL: test3:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r4, r4, 12
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; P9-NEXT: lxvwsx vs0, 0, r4
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; P9-NEXT: stxv vs0, 0(r3)
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; P9-NEXT: blr
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;
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; P8-LABEL: test3:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addi r4, r4, 12
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; P8-NEXT: lfiwzx f0, 0, r4
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; P8-NEXT: xxspltw v2, vs0, 1
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; P8-NEXT: stvx v2, 0, r3
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; P8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 3
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%0 = load i32, i32* %arrayidx, align 4
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%splat.splatinsert.i = insertelement <4 x i32> undef, i32 %0, i32 0
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%splat.splat.i = shufflevector <4 x i32> %splat.splatinsert.i, <4 x i32> undef, <4 x i32> zeroinitializer
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store <4 x i32> %splat.splat.i, <4 x i32>* %c, align 16
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ret void
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}
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define dso_local void @test4(<2 x i64>* nocapture %c, i64* nocapture readonly %a) local_unnamed_addr {
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; P9-LABEL: test4:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r4, r4, 24
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; P9-NEXT: lxvdsx vs0, 0, r4
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; P9-NEXT: stxv vs0, 0(r3)
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; P9-NEXT: blr
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;
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; P8-LABEL: test4:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addi r4, r4, 24
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; P8-NEXT: lxvdsx vs0, 0, r4
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; P8-NEXT: stxvd2x vs0, 0, r3
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; P8-NEXT: blr
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entry:
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%arrayidx = getelementptr inbounds i64, i64* %a, i64 3
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%0 = load i64, i64* %arrayidx, align 8
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%splat.splatinsert.i = insertelement <2 x i64> undef, i64 %0, i32 0
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%splat.splat.i = shufflevector <2 x i64> %splat.splatinsert.i, <2 x i64> undef, <2 x i32> zeroinitializer
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store <2 x i64> %splat.splat.i, <2 x i64>* %c, align 16
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ret void
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}
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define <16 x i8> @unadjusted_lxvwsx(i32* %s, i32* %t) {
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; P9-LABEL: unadjusted_lxvwsx:
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; P9: # %bb.0: # %entry
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: unadjusted_lxvwsx:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lfiwzx f0, 0, r3
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; P8-NEXT: xxspltw v2, vs0, 1
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; P8-NEXT: blr
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entry:
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%0 = bitcast i32* %s to <4 x i8>*
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%1 = load <4 x i8>, <4 x i8>* %0, align 4
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%2 = shufflevector <4 x i8> %1, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %2
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}
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define <16 x i8> @adjusted_lxvwsx(i64* %s, i64* %t) {
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; P9-LABEL: adjusted_lxvwsx:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r3, r3, 4
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: adjusted_lxvwsx:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lfdx f0, 0, r3
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; P8-NEXT: xxspltw v2, vs0, 0
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; P8-NEXT: blr
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entry:
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%0 = bitcast i64* %s to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 8
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%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %2
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}
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define <16 x i8> @unadjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: unadjusted_lxvwsx_v16i8:
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; P9: # %bb.0: # %entry
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: unadjusted_lxvwsx_v16i8:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lvx v2, 0, r3
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; P8-NEXT: xxspltw v2, v2, 3
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <16 x i8> %1
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}
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define <16 x i8> @adjusted_lxvwsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: adjusted_lxvwsx_v16i8:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r3, r3, 4
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: adjusted_lxvwsx_v16i8:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lvx v2, 0, r3
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; P8-NEXT: xxspltw v2, v2, 2
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %1
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}
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define <16 x i8> @adjusted_lxvwsx_v16i8_2(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: adjusted_lxvwsx_v16i8_2:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r3, r3, 8
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: adjusted_lxvwsx_v16i8_2:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lvx v2, 0, r3
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; P8-NEXT: xxspltw v2, v2, 1
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11>
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ret <16 x i8> %1
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}
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define <16 x i8> @adjusted_lxvwsx_v16i8_3(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: adjusted_lxvwsx_v16i8_3:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r3, r3, 12
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; P9-NEXT: lxvwsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: adjusted_lxvwsx_v16i8_3:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lvx v2, 0, r3
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; P8-NEXT: xxspltw v2, v2, 0
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %1
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}
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define <16 x i8> @unadjusted_lxvdsx(i64* %s, i64* %t) {
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; P9-LABEL: unadjusted_lxvdsx:
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; P9: # %bb.0: # %entry
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; P9-NEXT: lxvdsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: unadjusted_lxvdsx:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lxvdsx v2, 0, r3
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; P8-NEXT: blr
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entry:
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%0 = bitcast i64* %s to <8 x i8>*
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%1 = load <8 x i8>, <8 x i8>* %0, align 8
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%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %2
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}
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define <16 x i8> @unadjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: unadjusted_lxvdsx_v16i8:
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; P9: # %bb.0: # %entry
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; P9-NEXT: lxvdsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: unadjusted_lxvdsx_v16i8:
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; P8: # %bb.0: # %entry
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; P8-NEXT: lxvdsx v2, 0, r3
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <16 x i8> %1
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}
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define <16 x i8> @adjusted_lxvdsx_v16i8(<16 x i8> *%s, <16 x i8> %t) {
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; P9-LABEL: adjusted_lxvdsx_v16i8:
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; P9: # %bb.0: # %entry
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; P9-NEXT: addi r3, r3, 8
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; P9-NEXT: lxvdsx v2, 0, r3
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; P9-NEXT: blr
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;
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; P8-LABEL: adjusted_lxvdsx_v16i8:
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; P8: # %bb.0: # %entry
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; P8-NEXT: addi r3, r3, 8
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; P8-NEXT: lxvdsx v2, 0, r3
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; P8-NEXT: blr
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entry:
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%0 = load <16 x i8>, <16 x i8>* %s, align 16
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%1 = shufflevector <16 x i8> %0, <16 x i8> undef, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %1
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}
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