Eli Friedman 62028b7323 Fix the run-line for this test to work correctly outside of x86. ... llvm-svn: 73025		2009-06-07 09:44:19 +00:00
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Alpha
ARM	Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.	2009-06-05 19:08:58 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
CPP	Fix code emission for conditional branches.	2009-05-04 19:10:38 +00:00
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec	2009-06-07 01:07:55 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
X86	Fix the run-line for this test to work correctly outside of x86.	2009-06-07 09:44:19 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00