Sanjay Patel 62d8ec1120 [x86] enable storeOfVectorConstantIsCheap() target hook ... This allows vector-sized store merging of constants in DAGCombiner using the existing code in MergeConsecutiveStores(). All of the twisted logic that decides exactly what vector operations are legal and fast for each particular CPU are handled separately in there using the appropriate hooks. For the motivating tests in merge-store-constants.ll, we already produce the same vector code in IR via the SLP vectorizer. So this is just providing a backend backstop for code that doesn't go through that pass (-O1). More details in PR24449: https://bugs.llvm.org/show_bug.cgi?id=24449 (this change should be the last step to resolve that bug) Differential Revision: https://reviews.llvm.org/D37451 llvm-svn: 313458		2017-09-16 13:29:12 +00:00
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AArch64	[AArch64] allow v8f16 types when FullFP16 is supported	2017-09-15 09:24:48 +00:00
AMDGPU	AMDGPU: Fix violating constant bus restriction	2017-09-14 20:54:29 +00:00
ARC
ARM	Add newline to end of test file. NFC.	2017-09-14 14:48:59 +00:00
AVR
BPF	bpf: add " ll" in the LD_IMM64 asmstring	2017-09-11 23:43:35 +00:00
Generic
Hexagon	[IfConversion] More simple, correct dead/kill liveness handling	2017-09-14 15:53:11 +00:00
Inputs
Lanai
Mips	[mips] Pick the right variant of DINS upfront and enable target instruction verification	2017-09-14 10:58:00 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC	[XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map	2017-09-14 07:08:23 +00:00
SPARC
SystemZ	Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place.	2017-09-14 00:03:23 +00:00
Thumb
Thumb2
WebAssembly	[WebAssembly] Add sign extend instructions from atomics proposal	2017-09-13 00:29:06 +00:00
WinEH
X86	[x86] enable storeOfVectorConstantIsCheap() target hook	2017-09-16 13:29:12 +00:00
XCore