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llvm-mirror/test/CodeGen/Thumb/optionaldef-scheduling.ll
Artyom Skrobov b4dd4740ca [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs
Summary:
D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units.

Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC.

Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin

Reviewed By: javed.absar

Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB

Differential Revision: https://reviews.llvm.org/D31081

llvm-svn: 301106
2017-04-23 06:58:08 +00:00

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541 B
LLVM

; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s
; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s
define i1 @test(i64 %arg) {
entry:
%ispos = icmp sgt i64 %arg, -1
%neg = sub i64 0, %arg
%sel = select i1 %ispos, i64 %arg, i64 %neg
%cmp2 = icmp eq i64 %sel, %arg
ret i1 %cmp2
}
; The scheduler used to ignore OptionalDefs, and could unwittingly insert
; a flag-setting instruction in between an ADDS and the corresponding ADC.
; CHECK: adds
; CHECK-NOT: eors
; CHECK: adcs